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Register a new userThe studying of reduce the possible consumption in CMOS by Reduction Of switching Activity
دراسة إمكانية تخفيض الاستطاعة المستهلكة في دارات CMOS بإنقاص فعالية التبديل
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Tishreen University ورقة بحثية
Publication date
2018
fields
Communication Engineering
and research's language is
العربية
Authors
أحلام محمود محمود( باحث )
Created by
Shamra Editor
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يهدف البحث إلى دراسة تخفيض الاستطاعة المستهلكة في الدارات الرقمية نوع CMOS و إلى تطوير طرق جديدة في هذا المجال و الحصول على نتائج عملية جديدة قابلة للتطبيق في مجال تطوير الأجهزة الإلكترونية المتكاملة عالية الاندماج VLSI ، تم في هذا البحث دراسة تخفيض الاستطاعة المستهلكة الديناميكية بتخفيض فعالية التبديل حيث تم تغيير البنية الهندسية للدارة الرقمية على الاستطاعة المستهلكة ، و استخدمت تراكيب مختلفة للدارة. حيث تم الحصول على نتائج جيدة بطريقة المحاكاة باستخدام برنامج ال Matlab حيث تم تخفيض قدره 10 %مما يساعد ف تحقيق مواصفات عالية في تصميم الدارات.
This research aims to reduce the possible consumption in CMOS digital circuit type and to develop new methods in this area and get the results of a new process applicable in the field of the development of integrated electronic devices of high integration VLSI, has been in this study the possible reduction of consumer dynamic by Reduction Of switching Activit where the researcher changed the architecture of digital circuit on the possible consuming, and she used different combinations of the circuit. the researcher got good results in a manner using the Matlab simulation program where she got reduction of 01%, which helps us to achieve high standards in the design of integrated circuits.
References used
NAJM, F. "A survey of power estimation techniques in VLSI circuits," IEEE Transactions on VLSI Systems, vol. 2, December8105,pp. 446-455
HAYES & Horowitz."Field-E_ect (FET) transistors" .2013,(pp 142-162 and 244-266), Spring
OLEVEIRA Pinto, R.L.; Schneider, M.C; and Montoro, C.G. Sizing of MOS transistors for amplifier design. ISCAS, 2013
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