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Register a new userMOSFET Characterization and Modeling at Cryogenic Temperatures
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Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes. However, CMOS characteristics for various width/length (W/L) ratios and under different bias conditions still require further research. In addition, no previous works have produced an integrated modeling process for cryo-CMOS technology. In this paper, the results of characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18 {mu}m CMOS technology at cryogenic temperatures (varying from 300 K to 4.2 K) are presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with different W/L ratios are taken under four distinct bias conditions and at different temperatures. The temperature-dependent parameters are revised and an advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen temperature (LNT). The proposed model ensures precision at the LNT and is valid for use in an industrial tape-out process. The proposed method presents a calibration approach for BSIM3v3 that is available at different temperature intervals.
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This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 um from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.
Kink effect is a large obstacle for the cryogenic model of inversion-type bulk silicon MOSFET devices. This letter used two methods to correct the kink effect: the modified evolutionary strategy (MES) and dual-model modeling (BSIM3v3 and EKV2.6). Both methods are based on the principle of kink effect. The first method considers impact ionization and substrate current induced body effect (SCBE), and the other considers the change of the freeze-out substrate potential. By applying the above two methods, kink can be corrected to improve the agreement between simulation data and measurement data, and obtain more accurate model parameters. These two methods can be used in further work for cryogenic device modeling and circuit design.
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poissons equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28-nm CMOS process. The developed model is a key element for a cryo-CMOS compact model and can serve as a guide to optimize processes for high-performance cryo-computing and ultra-low-power quantum computing.
Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.
In this work, magnetization dynamics is studied at low temperatures in a hybrid system that consists of thin epitaxial magnetic film coupled with superconducting planar microwave waveguide. The resonance spectrum was observed in a wide magnetic field range, including low fields below the saturation magnetization and both polarities. Analysis of the spectrum via a developed fitting routine allowed to derive all magnetic parameters of the film at cryogenic temperatures, to detect waveguide-induced uniaxial magnetic anisotropies of the first and the second order, and to uncover a minor misalignment of magnetic field. A substantial influence of the superconducting critical state on resonance spectrum is observed and discussed.
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