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Register a new userCryogenic Modeling of MOSFET Device Based on BSIM and EKV Models
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Kink effect is a large obstacle for the cryogenic model of inversion-type bulk silicon MOSFET devices. This letter used two methods to correct the kink effect: the modified evolutionary strategy (MES) and dual-model modeling (BSIM3v3 and EKV2.6). Both methods are based on the principle of kink effect. The first method considers impact ionization and substrate current induced body effect (SCBE), and the other considers the change of the freeze-out substrate potential. By applying the above two methods, kink can be corrected to improve the agreement between simulation data and measurement data, and obtain more accurate model parameters. These two methods can be used in further work for cryogenic device modeling and circuit design.
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Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes. However, CMOS characteristics for various width/length (W/L) ratios and under different bias conditions still require further research. In addition, no previous works have produced an integrated modeling process for cryo-CMOS technology. In this paper, the results of characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18 {mu}m CMOS technology at cryogenic temperatures (varying from 300 K to 4.2 K) are presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with different W/L ratios are taken under four distinct bias conditions and at different temperatures. The temperature-dependent parameters are revised and an advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen temperature (LNT). The proposed model ensures precision at the LNT and is valid for use in an industrial tape-out process. The proposed method presents a calibration approach for BSIM3v3 that is available at different temperature intervals.
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poissons equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28-nm CMOS process. The developed model is a key element for a cryo-CMOS compact model and can serve as a guide to optimize processes for high-performance cryo-computing and ultra-low-power quantum computing.
In this perspective, we explore the insights into the device physics of perovskite solar cells gained from modeling and simulation of these devices. We discuss a range of factors that influence the modeling of perovskite solar cells, including the role of ions, dielectric constant, density of states, and spatial distribution of recombination losses. By focusing on the effect of non-ideal energetic alignment in perovskite photovoltaic devices, we demonstrate a unique feature in low recombination perovskite materials - the formation of an interfacial, primarily electronic, self-induced dipole that results in a significant increase in the built-in potential and device open-circuit voltage. Finally, we discuss the future directions of device modeling in the field of perovskite photovoltaics, describing some of the outstanding open questions in which device simulations can serve as a particularly powerful tool for future advancements in the field.
Reliable operation of photonic integrated circuits at cryogenic temperatures would enable new capabilities for emerging computing platforms, such as quantum technologies and low-power cryogenic computing. The silicon-on-insulator platform is a highly promising approach to developing large-scale photonic integrated circuits due to its exceptional manufacturability, CMOS compatibility and high component density. Fast, efficient and low-loss modulation at cryogenic temperatures in silicon, however, remains an outstanding challenge, particularly without the addition of exotic nonlinear optical materials. In this paper, we demonstrate DC-Kerr-effect-based modulation at a temperature of 5 K at GHz speeds, in a silicon photonic device fabricated exclusively within a CMOS process. This work opens up the path for the integration of DC Kerr modulators in large-scale photonic integrated circuits for emerging cryogenic classical and quantum computing applications.
This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 um from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.
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