No Arabic abstract
Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.
We propose paramagnetic semiconductors as active media for refrigeration at cryogenic temperatures by adiabatic demagnetization. The paramagnetism of impurity dopants or structural defects can provide the entropy necessary for refrigeration at cryogenic temperatures. We present a simple model for the theoretical limitations to specific entropy and cooling power achievable by demagnetization of various semiconductor systems. Performance comparable to that of the hydrate (CMN) is predicted.
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes. However, CMOS characteristics for various width/length (W/L) ratios and under different bias conditions still require further research. In addition, no previous works have produced an integrated modeling process for cryo-CMOS technology. In this paper, the results of characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18 {mu}m CMOS technology at cryogenic temperatures (varying from 300 K to 4.2 K) are presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with different W/L ratios are taken under four distinct bias conditions and at different temperatures. The temperature-dependent parameters are revised and an advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen temperature (LNT). The proposed model ensures precision at the LNT and is valid for use in an industrial tape-out process. The proposed method presents a calibration approach for BSIM3v3 that is available at different temperature intervals.
We predict it is possible to achieve high-efficiency room-temperature spin injection from a mag- netic metal into InAs-based semiconductors using an engineered Schottky barrier based on an InAs/AlSb superlattice. The Schottky barrier with most metals is negative for InAs and positive for AlSb. For such metals there exist InAs/AlSb superlattices with a conduction band edge perfectly aligned with the metals Fermi energy. The initial AlSb layer can be grown to the thickness required to produce a desired interface resistance. We show that the conductivity and spin lifetimes of such superlattices are sufficiently high to permit efficient spin injection from ferromagnetic metals.
In this study, a model of a Schottky-barrier carbon nanotube field- effect transistor (CNT-FET), with ferromagnetic contacts, has been developed. The emphasis is put on analysis of current-voltage characteristics as well as shot (and thermal) noise. The method is based on the tight-binding model and the non- equilibrium Greens function technique. The calculations show that, at room temperature, the shot noise of the CNT FET is Poissonian in the sub-threshold region, whereas in elevated gate and drain/source voltage regions the Fano factor gets strongly reduced. Moreover, transport properties strongly depend on relative magnetization orientations in the source and drain contacts. In particular, one observes quite a large tunnel magnetoresistance, whose absolute value may exceed 50%.
The transversal and longitudinal resistance in the quantum Hall effect regime was measured in a Si MOSFET sample in which a slot-gate allows one to vary the electron density and filling factor in different parts of the sample. In case of unequal gate voltages, the longitudinal resistances on the opposite sides of the sample differ from each other because the originated Hall voltage difference is added to the longitudinal voltage only on one side depending on the gradient of the gate voltages and the direction of the external magnetic field. After subtracting the Hall voltage difference, the increase in longitudinal resistance is observed when electrons on the opposite sides of the slot occupy Landau levels with different spin orientations.