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Register a new userCharacterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures
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P. A. t Hart
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This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 um from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full self-heating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.
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Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes. However, CMOS characteristics for various width/length (W/L) ratios and under different bias conditions still require further research. In addition, no previous works have produced an integrated modeling process for cryo-CMOS technology. In this paper, the results of characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18 {mu}m CMOS technology at cryogenic temperatures (varying from 300 K to 4.2 K) are presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with different W/L ratios are taken under four distinct bias conditions and at different temperatures. The temperature-dependent parameters are revised and an advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen temperature (LNT). The proposed model ensures precision at the LNT and is valid for use in an industrial tape-out process. The proposed method presents a calibration approach for BSIM3v3 that is available at different temperature intervals.
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4,K and 4.2,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18{mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18{mu}m standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of large and thin-oxide devices at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems.
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.
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