يهدف هذا المشروع إلى توصيف و تنفيذ تصميم عتادي لخوارزمية المسح باستخدام دارة قابلة للبرمجة FPGA ، بحيث يستطيع هذا التصميم أن يمسح صور بدقة عالية في الزمن الحقيقي، على الرغم من أن خوارزمية المسح خوارزمية تعمية كتلية. جرى اختيار كتل بقياس 256x256 بيكسل لتأمنٌ معدّل معطيات مناسب للعمل بالزمن الحقيقي. وقع الاختيار على تقنية
FPGA لبناء الكيان الصلب لهذه الخوارزمية، لما تتمتع به من إمكانيات هائلة في الحجم و السرعة.
No English abstract
References used
Roshni Padate, Aamna Patel. “Image encryption and decryption using AES algorithm”, INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION NGINEERING & TEcHNOLOGY (IJECET), 2015
M.A. Murillo-Escoba, C. Cruz-Hernández, F. Abundiz-Pérez, R.M. López-Gutiérrez, O.R. Acosta Del Campo. “A RGB image encryption algorithm based on total plain image characteristics and chaos”, ScienceDirect, Signal Processing , Volume 109, April 2015, Pages 119–131
Yuanmei Wang, Tao Li. “Study on Image Encryption Algorithm Based on Arnold Transformation and Chaotic System”, IEEE, Intelligent System Design and Engineering Application (ISDEA), 2011
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user.
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