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تسجيل مستخدم جديدDeep-recessed $beta$-Ga$_2$O$_3$ delta-doped field effect transistors with in situ epitaxial passivation
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We introduce a deep-recessed gate architecture in $beta$-Ga$_2$O$_3$ delta-doped field effect transistors for improvement in DC-RF dispersion and breakdown properties. The device design incorporates an unintentionally doped $beta$-Ga$_2$O$_3$ layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl$_3$ plasma based etching at ~5 W RIE to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 $deg$C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee-walkout at high V$_mathrm{DS}$, and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three terminal off-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated field effect transistors is a significant step for $beta$-Ga$_2$O$_3$ technology since the structure simultaneously provides control of surface-related dispersion and excellent field management.
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$beta$-Ga$_2$O$_3$ is a promising ultra-wide bandgap semiconductor whose properties can be further enhanced by alloying with Al. Here, using atomic-resolution scanning transmission electron microscopy (STEM), we find the thermodynamically-unstable $g
amma$-phase is a ubiquitous defect in both $beta$-(Al$_x$Ga$_{1text{-}x}$)$_2$O$_3$ films and doped $beta$-Ga$_2$O$_3$ films grown by molecular beam epitaxy. For undoped $beta$-(Al$_x$Ga$_{1text{-}x}$)$_2$O$_3$ films we observe $gamma$-phase inclusions between nucleating islands of the $beta$-phase at lower growth temperatures (~400-600 $^{circ}$C). In doped $beta$-Ga$_2$O$_3$, a thin layer of the $gamma$-phase is observed on the surfaces of films grown with a wide range of n-type dopants and dopant concentrations. The thickness of the $gamma$-phase layer was most strongly correlated with the growth temperature, peaking at about 600 $^{circ}$C. Ga interstitials are observed in $beta$-phase, especially near the interface with the $gamma$-phase. By imaging the same region of the surface of a Sn-doped $beta$-(Al$_x$Ga$_{1text{-}x}$)$_2$O$_3$ after ex-situ heating up to 400 $^{circ}$C, a $gamma$-phase region is observed to grow above the initial surface, accompanied by a decrease in Ga interstitials in the $beta$-phase. This suggests that the diffusion of Ga interstitials towards the surface is likely the mechanism for growth of the surface $gamma$-phase, and more generally that the more-open $gamma$-phase may offer diffusion pathways to be a kinetically-favored and early-forming phase in the growth of Ga$_2$O$_3$.
Recent breakthroughs in bulk crystal growth of the thermodynamically stable beta phase of gallium oxide ($beta$-Ga$_2$O$_3$) have led to the commercialization of large-area beta-Ga$_2$O$_3$ substrates with subsequent epitaxy on (010) substrates produ
cing high-quality films. Still, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and processing of the (010) $beta$-Ga$_2$O$_3$ surface are known to form sub-nanometer scale facets along the [001] direction as well as larger ridges with features perpendicular to the [001] direction. A density function theory calculation of the (010) surface shows an ordering of the surface as a sub-nanometer-scale feature along the [001] direction. Additionally, the general crystal structure of $beta$-Ga$_2$O$_3$ is presented and recommendations are presented for standardizing (010) substrates to account for and control the larger-scale ridge formation.
A comprehensive study of drain current dispersion effects in $beta$-Ga$_2$O$_3$ FETs has been done using DC, pulsed and RF measurements. Both virtual gate effect in the gate-drain access region and interface traps under the gate are most plausible ex
planations for the experimentally observed pulsed current dispersion and high temperature threshold voltage shift respectively. Unpassivated devices show significant current dispersion between DC and pulsed IV response due to gate lag effect characterized by time constants in the range of 400~$mu s$ to 600~$mu s$. An activation energy of 99~$meV$ is estimated from temperature dependent Arrhenius plots. A variable range hopping based slow transport in conjunction with the observed shallow trap level is attributed to the observed slow transient response of drain current with respect to time. Reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. Effect of traps can be minimized by using surface passivation layers, in this case, Silicon Nitride which shows significant improvement in the current dispersion and RF cutoff frequency. This work demonstrates the detrimental effect the traps can have on the current dispersion which significantly limits the high frequency operation of the device.
Based on first-principles calculations, we show that the maximum reachable concentration $x$ in the (Ga$_{1-x}$In$_x$)$_2$O$_3$ alloy in the low-$x$ regime (i.e. In solubility in $beta$-Ga$_2$O$_3$) is around 10%. We then calculate the band alignment
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btained for both forward and reverse gate voltage sweeps with a minimum value of 34.3 mV/dec at reverse gate voltage sweep and 53.1 mV/dec at forward gate voltage sweep at $V_{DS}$=0.5 V. Enhancement-mode operation with threshold voltage ~0.4 V is achieved by tuning the thickness of $beta$-Ga$_2$O$_3$ membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis and enhancement-mode $beta$-Ga$_2$O$_3$ NC-FETs are promising as nFET candidate for future wide bandgap CMOS logic applications.
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