Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode
is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.
Presented in this paper is a proof-of-concept for a new approach to single electron pumping based on a Single Atom Transistor (SAT). By charge pumping electrons through an isolated dopant atom in silicon, precise currents of up to 160 pA at 1 GHz are
generated, even if operating at 4.2 K, with no magnetic field applied, and only when one barrier is addressed by sinusoidal voltage cycles.
This paper discusses how classical transport theories such as the thermionic emission, can be used as a powerful tool for the study and the understanding of the most complex mechanisms of transport in Fin Field Effect Transistors (FinFETs). By means
of simple current and differential conductance measurements, taken at different temperatures and different gate voltages ($V_G$s), it is possible to extrapolate the evolution of important parameters such as the spatial region of transport and the height of thermionic barrier at the centre of the channel. Furthermore, if the measurements are used in conjunction with simulated data, it becomes possible to also extract the interface trap density of these objects. These are important results, also because these parameters are extracted directly on state-of-the-art devices and not in specially-designed test structures. The possible characterisation of the different regimes of transport that can arise in these ultra-scaled devices having a doped or an undoped channel are also discussed. Examples of these regimes are, full body inversion and weak body inversion. Specific cases demonstrating the strength of the thermionic tool are discussed in sections ref{sec:II}, ref{sec:III} and ref{sec:IV}. This text has been designed as a comprehensive overview of 4 related publications (see Ref. [2-5]) and has been submitted as a book chapter in Ref. [6]).
Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. This paper describes how, through correlation of experimental data with multimillion atom tight-binding simulations usin
g the NEMO 3-D code, it is possible to identify the impuritys chemical species and determine their concentration, local electric field and depth below the Si/SiO$_{mathrm{2}}$ interface. The ability to model the excited states rather than just the ground state is the critical component of the analysis and allows the demonstration of a new approach to atomistic impurity metrology.
Semiconductor nano-devices have been scaled to the level that transport can be dominated by a single dopant atom. In the strong coupling case a Kondo effect is observed when one electron is bound to the atom. Here, we report on the spin as well as or
bital Kondo ground state. We experimentally as well than theoretically show how we can tune a symmetry transition from a SU(4) ground state, a many body state that forms a spin as well as orbital singlet by virtual exchange with the leads, to a pure SU(2) orbital ground state, as a function of magnetic field. The small size and the s-like orbital symmetry of the ground state of the dopant, make it a model system in which the magnetic field only couples to the spin degree of freedom and allows for observation of this SU(4) to SU(2) transition.
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods
for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.
Thermally activated sub-threshold transport has been investigated in undoped triple gate MOSFETs. The evolution of the barrier height and of the active cross-section area of the channel as a function of gate voltage has been determined. The results o
f our experiments and of the Tight Binding simulations we have developed are both in good agreement with previous analytical calculations, confirming the validity of thermionic approach to investigate transport in FETs. This method provides an important tool for the improvement of devices characteristics.
Focused ion beam (FIB) technology has been used to fabricate miniature Nb DC SQUIDs which incorporate resistively-shunted microbridge junctions and a central loop with a hole diameter ranging from 1058 nm to 50 nm. The smallest device, with a 50 nm h
ole diameter, has a white flux noise level of 2.6 microphy_{0}/Hz^{0.5} at 10^{4} Hz. The scaling of the flux noise properties and focusing effect of the SQUID with the hole size were examined. The observed low-frequency flux noise of different devices were compared with the contribution due to the spin fluctuation of defects during FIB processing and the thermally activated flux hopping in the SQUID washer.
In this communication we present our response to the recent comment of A. Engel regarding our paper on FIB- fabricated Nb nanowires (see Vol. 20 (2009) Pag. 465302). After further analysis and additional experimental evidence, we conclude that our in
terpretation of the experimental results in light of QPS theory is still valid when compared with the alternative proximity-based model as proposed by A. Engel.
Making use of focused Ga-ion beam (FIB) fabrication technology, the evolution with device dimension of the low-temperature electrical properties of Nb nanowires has been examined in a regime where crossover from Josephson-like to insulating behaviour
is evident. Resistance-temperature data for devices with a physical width of order 100 nm demonstrate suppression of superconductivity, leading to dissipative behaviour that is shown to be consistent with the activation of phase-slip below Tc. This study suggests that by exploiting the Ga-impurity poisoning introduced by the FIB into the periphery of the nanowire, a central superconducting phase-slip nanowire with sub-10 nm dimensions may be engineered within the core of the nanowire.
