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Register a new userDevelopment of ultra-light pixelated ladders for an ILC vertex detector
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Added by
Nathalie Chon-Sen Dr
Publication date
2010
fields
Physics
and research's language is
English
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The development of ultra-light pixelated ladders is motivated by the requirements of the ILD vertex detector at ILC. This paper summarizes three projects related to system integration. The PLUME project tackles the issue of assembling double-sided ladders. The SERWIETE project deals with a more innovative concept and consists in making single-sided unsupported ladders embedded in an extra thin plastic enveloppe. AIDA, the last project, aims at building a framework reproducing the experimental running conditions where sets of ladders could be tested.
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We discuss two projects exploring the integration of thin CMOS pixel sensors in order to prototype ladders matching the geometry needed for the ILD vertex detector. The PLUME project has designed and fabricated full-size and fully functional double- sided layers which currently reach 0.6 % X0 and aim for 0.3 % X0 in mid-2012. Another approach, SERNWIETE, consists in wrapping the sensors in a polyimide-based micro-cable to obtain a supportless single-sided ladder with a material budget around 0.15 % X0. First promising samples have been produced and the full-size prototype is expected in spring 2012.
We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.
A pixel detector with high spatial resolution and temporal information for ultra-cold neutrons is developed based on a commercial CCD on which a neutron converter is attached. 10B and 6Li are tested for the neutron converter and 10B is found to be more suitable based on efficiency and spatial resolution. The pixel detector has an efficiency of 44.1 +- 1.1% and a spatial resolution of 2.9 +- 0.1 um (1 sigma).
CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.
One of candidates for the International Linear Collider(ILC)s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 times 5 (mum^2). Sensor and readout systems are currently being studied and prototypes have been developed. In this paper we will report on the performance of latest developed readout ASIC prototype as well as the outline of the design strategy for the next ASIC prototype.
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