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Register a new userDevelopment of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements
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CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.
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The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.
Purpose: CMOS pixel sensors have become extremely attractive for future high performance tracking devices. Initial R&D work has been conducted for the vertex detector for the proposed Circular Electron Positron Collider that will allow precision Higgs measurements. It is critical to achieve low power consumption to minimize the material budget. This requires careful optimization of the sensor diode geometry to reach high charge-over-capacitance that allows reduction in analog power consumption. Methods: The electrode area and footprint are two critical elements in sensor diode geometry and have deciding impacts on the sensor charge collection performance. Prototype CMOS pixel sensor JadePix-1 has been developed with pixel sectors implementing different electrode area and footprint and their charge collection performance has been characterized with radioactive resources. Results: Charge-to-voltage conversion gains are calibrated with low energy X-ray. Noise, charge collection efficiency, charge-over-capacitance and signal-to-noise ratio are obtained for pixel sectors of different electrode area and footprint. Conclusion: Small electrode area and large footprint are preferred to achieve high charge-over-capacitance that promises low analog power consumption. Ongoing studies on sensor performance before and after irradiation, combined with this work, will conclude on the diode geometry optimization.
CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($sim 20 mu m$) and low material budget ($sim 0.2-0.3% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity epitaxial layers leads to the better radiation hardness and allows the implementation of accelerated readout circuits. The TowerJazz $0.18 mu m$ CMOS process being one of the most relevant examples recently became of interest for several future detector projects. The most imminent of these project is an upgrade of the Inner Tracking System (ITS) of the ALICE detector at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems.
We discuss two projects exploring the integration of thin CMOS pixel sensors in order to prototype ladders matching the geometry needed for the ILD vertex detector. The PLUME project has designed and fabricated full-size and fully functional double- sided layers which currently reach 0.6 % X0 and aim for 0.3 % X0 in mid-2012. Another approach, SERNWIETE, consists in wrapping the sensors in a polyimide-based micro-cable to obtain a supportless single-sided ladder with a material budget around 0.15 % X0. First promising samples have been produced and the full-size prototype is expected in spring 2012.
The impact of the incoherent electron-positron pairs from beamstrahlung on the occupancy of the vertex detector (VXD) for the International Large Detector concept (ILD) has been studied, based on the standard ILD simulation tools. The occupancy was evaluated for two substantially different sensor technology in order to estimate the importance of the latter. The influence of an anti-DID field removing backscattered electrons has also been studied.
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