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Register a new userDevelopement of readout ASIC for FPCCD vertex detector
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One of candidates for the International Linear Collider(ILC)s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 times 5 (mum^2). Sensor and readout systems are currently being studied and prototypes have been developed. In this paper we will report on the performance of latest developed readout ASIC prototype as well as the outline of the design strategy for the next ASIC prototype.
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We are developing the vertex detector with a fine pixel CCD (FPCCD) for the international linear collider (ILC), whose pixel size is $5 times 5$ $mu$m$^{2}$. To evaluate the performance of the FPCCD vertex detector and optimize its design, development of the software dedicated for the FPCCD is necessary. We, therefore, started to develop the software for FPCCD. In this article, the status of the study is reported.
One of the major physics goals at the ILC is the precise measurement of the Higgs coupling constants to b-quarks and c-quarks. To achieve this measurement, we need a high-performance vertex detector leading to precise flavor tagging. For this purpose, we are developing the Fine Pixel CCD (FPCCD) vertex detector. In this paper, we will report on the development status of FPCCDTrackFinder, a new track finder improving tracking efficiency, especially in the low $p_t$ region, and an evaluation result of the flavor tagging performance with FPCCDTrackFinder in the FPCCD vertex detector.
We fabricated a readout ASIC with the fully depleted silicon-on-insulator (FD-SOI) technology for the pair-monitor. The pair-monitor is a silicon pixel device that measures the beam profile of the international linear collider. It utilizes the directional distribution of a large number of electron-positron pairs created by collision of bunches, and is required to tolerate radiation dose of about a few Mrad/year. The irradiation might cause the buried oxide layer of SOI to accumulate charges which interfere with intended functions. We thus performed extensive irradiation tests on the prototype ASIC, and the results are described in this paper.
Vertex detector cable requirements are considered within the context of the SiD concept. Cable material should be limited so that the number of radiation lengths represented is consistent with the material budget. In order to take advantage of the proposed accelerator beam structure and allow cooling by flow of dry gas, pulsed power is assumed. Potential approaches to power distribution, cable paths, and cable design for operation in a 5 T magnetic field are described.
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also presented in order to demonstrate the potential of the architecture as a reliable front-end readout electronic solution.
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