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Register a new userStatus of a DEPFET pixel system for the ILC vertex detector
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We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.
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The innermost part of the ATLAS experiment will be a pixel detector containing around 1750 individual detector modules. A detector control system (DCS) is required to handle thousands of I/O channels with varying characteristics. The main building blocks of the pixel DCS are the cooling system, the power supplies and the thermal interlock system, responsible for the ultimate safety of the pixel sensors. The ATLAS Embedded Local Monitor Board (ELMB), a multi purpose front end I/O system with a CAN interface, is foreseen for several monitoring and control tasks. The Supervisory, Control And Data Acquisition (SCADA) system will use PVSS, a commercial software product chosen for the CERN LHC experiments. We report on the status of the different building blocks of the ATLAS pixel DCS.
The development of ultra-light pixelated ladders is motivated by the requirements of the ILD vertex detector at ILC. This paper summarizes three projects related to system integration. The PLUME project tackles the issue of assembling double-sided ladders. The SERWIETE project deals with a more innovative concept and consists in making single-sided unsupported ladders embedded in an extra thin plastic enveloppe. AIDA, the last project, aims at building a framework reproducing the experimental running conditions where sets of ladders could be tested.
Fine pixel CCD (FPCCD) is one of the candidate sensor technologies for the vertex detector used for experiments at the International Linear Collider (ILC). FPCCD vertex detector is supposed to be cooled down to -40 degree for improvement of radiation immunity. For this purpose, a two-phase CO2 cooling system using a gas compressor for CO2 circulation is being developed at KEK. The status of this R&D is presented in this article.
The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 $mathrm{mathbf{mu m}}$. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling and services. In this paper the status of DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear $mathbf{e^+ e^-}$ collider.
The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection using a radioactive source. These results prove the functionality of the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify it can work up to about 3 Gbps. And it also indicates that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.
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