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Register a new userIDeF-X ASIC for Cd(Zn)Te spectro-imaging systems
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Joint progresses in Cd(Zn)Te detectors, microelectronics and interconnection technologies open the way for a new generation of instruments for physics and astrophysics applications in the energy range from 1 to 1000 keV. Even working between -20 and 20 degrees Celsius, these instruments will offer high spatial resolution (pixel size ranging from 300 x 300 square micrometers to few square millimeters), high spectral response and high detection efficiency. To reach these goals, reliable, highly integrated, low noise and low power consumption electronics is mandatory. Our group is currently developing a new ASIC detector front-end named IDeF-X, for modular spectro-imaging system based on the use of Cd(Zn)Te detectors. We present here the first version of IDeF-X which consists in a set of ten low noise charge sensitive preamplifiers (CSA). It has been processed with the standard AMS 0.35 micrometer CMOS technology. The CSA are designed to be DC coupled to detectors having a low dark current at room temperature. The various preamps implemented are optimized for detector capacitances ranging from 0.5 up to 30 pF.
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IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 microns process technology. Its power consumption is 800 micro watt per channel. The dynamic range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 micro seconds peak time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2 keV FWHM at 667 keV (137-Cs) on a mono-pixel configuration. Meanwhile, we also measured 562 eV and 666 eV FWHM at 14 keV and 60 keV respectively (241-Am) with a 256 small pixel array and a low detection threshold of 1.2 keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the Linear Energy Transfer threshold above 110 MeV/(mg/cm2). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high-energy resolution. The chip is space qualified and flies on board the Solar Orbiter ESA mission launched in 2020.
An innovative X-ray imaging sensor with intrinsic digital characteristics is presented. It is based on Chromatic Photon Counting technology. The detector is able to count individually the incident X-ray photons and to separate them according to their energy (two color images per exposure). The energy selection occurs in real time and at radiographic imaging speed (GHz global counting rate). Photon counting, color mode and a very high spatial resolution (more than 10 l.p./mm at MTF50) allow to obtain an optimal ratio between image quality and absorbed dose. The individual block of the imaging system is a two-side buttable semiconductor radiation detector made of a thin pixellated CdTe crystal (the sensor) coupled to a large area VLSI CMOS pixel ASIC. 1, 2, 4, 8 tile units have been built. The 8 tiles unit has 25cm x 2.5cm sensitive area. Results and images obtained from in depth testing of several configurations of the system are presented. The X-Ray imaging system is the technological platform of PIXIRAD Imaging Counters s.r.l., a recently constituted INFN spin-off company.
We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1 $mu$s peaking time and a temperature of 248 K, an electronic resolution of 13- and 10 electrons rms was measured with and without a SDD sensor respectively. A spectral resolution of 170 eV FWHM at 5.9 keV was obtained with an $^{55}$Fe source. The channel linearity was better than $pm$ 1 % with rate capabilities up to 40 kcps. The ASIC was fabricated in a commercial 250 nm process with a footprint of 6.3 mm x 3.9 mm and dissipates 167 mW of static power.
One of candidates for the International Linear Collider(ILC)s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 times 5 (mum^2). Sensor and readout systems are currently being studied and prototypes have been developed. In this paper we will report on the performance of latest developed readout ASIC prototype as well as the outline of the design strategy for the next ASIC prototype.
In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at 4.8 Gbps. LOCx2-130 can interface with three types of ADCs, an ASIC ADC and two COTS ADCs. LOCx2-130 is fabricated in a commercial 130-nm CMOS technology and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a latency of less than 40.7 ns.
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