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Register a new userDevelopment of a High Rate Front-end ASIC for X-ray Spectroscopy and Diffraction Applications
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We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1 $mu$s peaking time and a temperature of 248 K, an electronic resolution of 13- and 10 electrons rms was measured with and without a SDD sensor respectively. A spectral resolution of 170 eV FWHM at 5.9 keV was obtained with an $^{55}$Fe source. The channel linearity was better than $pm$ 1 % with rate capabilities up to 40 kcps. The ASIC was fabricated in a commercial 250 nm process with a footprint of 6.3 mm x 3.9 mm and dissipates 167 mW of static power.
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We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout channels, and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9 e- +/- 11.3 e- (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons within the energy from 6.4 keV to 122.1 keV are detected. Based on the experimental results, we propose a new low-noise readout architecture making use of a slew-rate limited mode at the shaper followed by a peak detector circuit.
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $mu$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180~nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695$pm$71~e$^-$ (rms) with a detector capacitance of 300~pF. The dynamic range was measured to be 20--100~fC in the low-gain mode and 200--1600~fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.
A 64-channel mixed-mode ASIC, suitable for particle detectors of large dynamic range and high capacitance up to hundreds of pF, is presented here. Each channel features an analogue front-end for signal amplification and filtering, and a mixed signal back-end to digitise and store the signal information. The analogue part consists of a low input-impedance programmable gain pre-amplifier based on a regulated common-gate (RCG) input stage, two shapers optimised for time and energy measurements. The back-end part mainly includes discriminators, TDCs and ADCs, which are used to process the signal and encode both the time of arrival and the charge in the input signal with a fully digital output. The programmable gain of the front-end (up to 400 fC input dynamic range) and the versatile back-end allow the readout of different gaseous detectors like GEM, MicroMEGAS and MWPC. The ASIC is designed for an event rate up to 100 kHz per channel and a power consumption less than 9 mW/channel, has been fabricated in a 110 nm CMOS technology.
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 um CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also presented in order to demonstrate the potential of the architecture as a reliable front-end readout electronic solution.
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