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IDeF-X HD: a CMOS ASIC for the readout of Cd(Zn)Te Detectors for space-borne applications

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 Added by Olivier Limousin
 Publication date 2021
  fields Physics
and research's language is English




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IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 microns process technology. Its power consumption is 800 micro watt per channel. The dynamic range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 micro seconds peak time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2 keV FWHM at 667 keV (137-Cs) on a mono-pixel configuration. Meanwhile, we also measured 562 eV and 666 eV FWHM at 14 keV and 60 keV respectively (241-Am) with a 256 small pixel array and a low detection threshold of 1.2 keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the Linear Energy Transfer threshold above 110 MeV/(mg/cm2). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high-energy resolution. The chip is space qualified and flies on board the Solar Orbiter ESA mission launched in 2020.



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Joint progresses in Cd(Zn)Te detectors, microelectronics and interconnection technologies open the way for a new generation of instruments for physics and astrophysics applications in the energy range from 1 to 1000 keV. Even working between -20 and 20 degrees Celsius, these instruments will offer high spatial resolution (pixel size ranging from 300 x 300 square micrometers to few square millimeters), high spectral response and high detection efficiency. To reach these goals, reliable, highly integrated, low noise and low power consumption electronics is mandatory. Our group is currently developing a new ASIC detector front-end named IDeF-X, for modular spectro-imaging system based on the use of Cd(Zn)Te detectors. We present here the first version of IDeF-X which consists in a set of ten low noise charge sensitive preamplifiers (CSA). It has been processed with the standard AMS 0.35 micrometer CMOS technology. The CSA are designed to be DC coupled to detectors having a low dark current at room temperature. The various preamps implemented are optimized for detector capacitances ranging from 0.5 up to 30 pF.
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