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Register a new userDesign and proof of concept for silicon-based quantum dot quantum bits
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Spins based in silicon provide one of the most promising architectures for quantum computing. Quantum dots are an inherently scalable technology. Here, we combine these two concepts into a workable design for a silicon-germanium quantum bit. The novel structure incorporates vertical and lateral tunneling, provides controlled coupling between dots, and enables single electron occupation of each dot. Precise modeling of the design elucidates its potential for scalable quantum computing. For the first time it is possible to translate the requirements of fault-tolerant error correction into specific requirements for gate voltage control electronics in quantum dots. We demonstrate that these requirements are met by existing pulse generators in the kHz-MHz range, but GHz operation is not yet achievable. Our calculations further pinpoint device features that enhance operation speed and robustness against leakage errors. We find that the component technologies for silicon quantum dot quantum computers are already in hand.
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Spins based in silicon provide one of the most promising architectures for quantum computing. A scalable design for silicon-germanium quantum dot qubits is presented. The design incorporates vertical and lateral tunneling. Simulations of a four-qubit array suggest that the design will enable single electron occupation of each dot of a many-dot array. Performing two-qubit operations has negligible effect on other qubits in the array. Simulation results are used to translate error correction requirements into specifications for gate-voltage control electronics. This translation is a necessary link between error correction theory and device physics.
The spin states of single electrons in gate-defined quantum dots satisfy crucial requirements for a practical quantum computer. These include extremely long coherence times, high-fidelity quantum operation, and the ability to shuttle electrons as a mechanism for on-chip flying qubits. In order to increase the number of qubits to the thousands or millions of qubits needed for practical quantum information we present an architecture based on shared control and a scalable number of lines. Crucially, the control lines define the qubit grid, such that no local components are required. Our design enables qubit coupling beyond nearest neighbors, providing prospects for non-planar quantum error correction protocols. Fabrication is based on a three-layer design to define qubit and tunnel barrier gates. We show that a double stripline on top of the structure can drive high-fidelity single-qubit rotations. Qubit addressability and readout are enabled by self-aligned inhomogeneous magnetic fields induced by direct currents through superconducting gates. Qubit coupling is based on the exchange interaction, and we show that parallel two-qubit gates can be performed at the detuning noise insensitive point. While the architecture requires a high level of uniformity in the materials and critical dimensions to enable shared control, it stands out for its simplicity and provides prospects for large-scale quantum computation in the near future.
Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction cite{Terhal2015}, enabling large-scale universal quantum computation.
We derive a general relation between the fine structure splitting (FSS) and the exciton polarization angle of self-assembled quantum dots (QDs) under uniaxial stress. We show that the FSS lower bound under external stress can be predicted by the exciton polarization angle and FSS under zero stress. The critical stress can also be determined by monitoring the change in exciton polarization angle. We confirm the theory by performing atomistic pseudopotential calculations for the InAs/GaAs QDs. The work provides a deep insight into the dots asymmetry and their optical properties, and a useful guide in selecting QDs with smallest FSS which are crucial in entangled photon sources applications.
RF reflectometry offers a fast and sensitive method for charge sensing and spin readout in gated quantum dots. We focus in this work on the implementation of RF readout in accumulation-mode gate-defined quantum dots, where the large parasitic capacitance poses a challenge. We describe and test two methods for mitigating the effect of the parasitic capacitance, one by on-chip modifications and a second by off-chip changes. We demonstrate that these methods enable high-performance charge readout in Si/SiGe quantum dots, achieving a fidelity of 99.9% for a measurement time of 1 $mu$s.
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