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Silicon CMOS architecture for a spin-based quantum computer

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 Added by Menno Veldhorst
 Publication date 2016
  fields Physics
and research's language is English




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Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (CMOS) technology, which is the basis for all modern processor chips. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin states of a single electron confined in a quantum dot, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout cite{Colless2013}. This system, based entirely on available technology and existing components, is compatible with general surface code quantum error correction cite{Terhal2015}, enabling large-scale universal quantum computation.



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Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot, fabricated using CMOS compatible processes at the 300 mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum dot charge sensor, measured using radiofrequency gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5-0.7 meV using excited state spectroscopy, and measure a maximum electron spin relaxation time ($T_1$) of $9 pm 3$ s at 1 Tesla. These long lifetimes indicate the silicon nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well-suited to a variety of scalable architectures.
We demonstrate how gradient ascent pulse engineering optimal control methods can be implemented on donor electron spin qubits in Si semiconductors with an architecture complementary to the original Kanes proposal. We focus on the high-fidelity controlled-NOT (CNOT) gate and explicitly find its digitized control sequences by optimizing its fidelity over the external controls of the hyperfine A and exchange J interactions. This high-fidelity CNOT gate has an error of about $10^{-6}$, below the error threshold required for fault-tolerant quantum computation, and its operation time of 100ns is about 3 times faster than 297ns of the proposed global control scheme. It also relaxes significantly the stringent distance constraint of two neighboring donor atoms of 10~20nm as reported in the original Kanes proposal to about 30nm in which surface A and J gates may be built with current fabrication technology. The effects of the control voltage fluctuations, the dipole-dipole interaction and the electron spin decoherence on the CNOT gate fidelity are also discussed.
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The idea of topological quantum computation (TQC) is to store and manipulate quantum information in an intrinsically fault-tolerant manner by utilizing the physics of topologically ordered phases of matter. Currently, one of the most promising platforms for a topological qubit is in terms of Majorana fermion zero modes (MZMs) in spin-orbit coupled superconducting nanowires. However, the topologically robust operations that are possible with MZMs can be efficiently simulated on a classical computer and are therefore not sufficient for realizing a universal gate set for TQC. Here, we show that an array of coupled semiconductor-superconductor nanowires with MZM edge states can be used to realize a more sophisticated type of non-Abelian defect: a genon in an Ising $times$ Ising topological state. This leads to a possible implementation of the missing topologically protected $pi/8$ phase gate and thus universal TQC based on semiconductor-superconductor nanowire technology. We provide detailed numerical estimates of the relevant energy scales, which we show to lie within accessible ranges.
Spins of donor electrons and nuclei in silicon are promising quantum bit (qubit) candidates which combine long coherence times with the fabrication finesse of the silicon nanotechnology industry. We outline a potentially scalable spin qubit architecture where donor nuclear and electron spins are coupled to spins of electrons in quantum dots and discuss requirements for donor placement aligned to quantum dots by single ion implantation.
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