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Register a new userRadiation-Tolerant, High-speed Serial Link Design with SRAM-based FPGAs
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High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due the sensitivity of SRAM-based FPGA to radiation faults (single event upsets). However, the device tolerance to radiation environments can be achieved by adopting dedicated mitigation techniques such as information redundancy, hardware redundancy and configuration scrubbing. In this work, we discuss the design of a bi-directional serial link running at 6.25 Gbps based on a Xilinx Kintex-7 FPGA. The link is protected against single event upsets by means of all the above-mentioned methods. A self-synchronizing scrambler is used for DC-balance and data randomization, while the subsequent Reed-Solomon encoder/decoder detects and corrects bursts of errors in the transmitted data. The error correction capability of the line code is further increased by adopting the interleaving technique. Besides, in order to completely take advantage of available bandwidth and to cope with different rates of radiation-induced faults, the link can modulate the protection level of the Reed-Solomon code. The reliability of the link is also improved by means of modular redundancy on the frame alignment block. Besides, on the same FPGA, a scrubber repairs corrupted configuration frames in real-time. We present the test results carried out using the fault injection method. We show the performance of the link in terms of mean time between failures (MTBF) and fault tolerance to upsets.
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We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA with 24 serial transceivers at 8.5 Gbps, together with a custom mezzanine hosting three QSFP+ modules. We present test results and signal integrity measurements up to an aggregated bandwidth of 12 Gbps.
An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper.
A PC based high speed silicon microstrip beam telescope consisting of several independent modules is presented. Every module contains an AC-coupled double sided silicon microstrip sensor and a complete set of analog and digital signal processing electronics. A digital bus connects the modules with the DAQ PC. A trigger logic unit coordinates the operation of all modules of the telescope. The system architecture allows easy integration of any kind of device under test into the data acquisition chain. Signal digitization, pedestal correction, hit detection and zero suppression are done by hardware inside the modules, so that the amount of data per event is reduced by a factor of 80 compared to conventional readout systems. In combination with a two level data acquisition scheme, this allows event rates up to 7.6 kHz. This is a factor of 40 faster than conventional VME based beam telescopes while comparable analog performance is maintained achieving signal to noise ratios of up to 70:1. The telescope has been tested in the SPS testbeam at CERN. It has been adopted as the reference instrument for testbeam studies for the ATLAS pixel detector development.
In this paper, we report on the radiation resistance of 50-micron thick LGAD detectors manufactured at the Fondazione Bruno Kessler employing several different doping combinations of the gain layer. LGAD detectors with gain layer doping of Boron, Boron low-diffusion, Gallium, Carbonated Boron and Carbonated Gallium have been designed and successfully produced. These sensors have been exposed to neutron fluences up to $phi_n sim 3 cdot 10^{16}; n/cm^2$ and to proton fluences up to $phi_p sim 9cdot10^{15}; p/cm^2$ to test their radiation resistance. The experimental results show that Gallium-doped LGADs are more heavily affected by initial acceptor removal than Boron-doped LGAD, while the presence of Carbon reduces initial acceptor removal both for Gallium and Boron doping. Boron low-diffusion shows a higher radiation resistance than that of standard Boron implant, indicating a dependence of the initial acceptor removal mechanism upon the implant width. This study also demonstrates that proton irradiation is at least twice more effective in producing initial acceptor removal, making proton irradiation far more damaging than neutron irradiation.
Belle II is a new-generation B-factory experiment, dedicated to exploring new physics beyond the standard model of elementary particles in the flavor sector. Belle~II started data-taking in April 2018, using a synchronous data acquisition (DAQ) system based on pipelined trigger flow control. The Belle II DAQ system is designed to handle a 30-kHz trigger rate with approximately 1% of dead time, under the assumption of a raw event size of 1 MB. The DAQ system is reliable, and the overall data-taking efficiency reached 84.2% during the run period of January 2020 to June 2020. The current readout system cannot be operated in the term of 10 years from the viewpoint of DAQ maintainability; meanwhile, the readout system is obstructing high-speed data transmission. A solution involving a PCI-express-based readout module with high data throughput of up to 100 Gb/s was adopted to upgrade the Belle II DAQ system. We particularly focused on the design of firmware and software based on this new generation of readout board, called PCIe40, with an Altera Arria 10 field-programmable gate array chip. Forty-eight GBT (GigaBit Transceiver) serial links, PCI-express hard IP-based DMA architecture, interface of timing and trigger distribution system, and slow control system were designed to integrate with the current Belle II DAQ system. This paper describes the performances accomplished during the data readout and slow control tests conducted using a test bench and a demonstration performed using on-site front-end electronics, specifically involving Belle II TOP and KLM sub-detectors.
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