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Register a new userActive inductor shunt peaking in high-speed VCSEL driver design
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An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper.
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High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due the sensitivity of SRAM-based FPGA to radiation faults (single event upsets). However, the device tolerance to radiation environments can be achieved by adopting dedicated mitigation techniques such as information redundancy, hardware redundancy and configuration scrubbing. In this work, we discuss the design of a bi-directional serial link running at 6.25 Gbps based on a Xilinx Kintex-7 FPGA. The link is protected against single event upsets by means of all the above-mentioned methods. A self-synchronizing scrambler is used for DC-balance and data randomization, while the subsequent Reed-Solomon encoder/decoder detects and corrects bursts of errors in the transmitted data. The error correction capability of the line code is further increased by adopting the interleaving technique. Besides, in order to completely take advantage of available bandwidth and to cope with different rates of radiation-induced faults, the link can modulate the protection level of the Reed-Solomon code. The reliability of the link is also improved by means of modular redundancy on the frame alignment block. Besides, on the same FPGA, a scrubber repairs corrupted configuration frames in real-time. We present the test results carried out using the fault injection method. We show the performance of the link in terms of mean time between failures (MTBF) and fault tolerance to upsets.
We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for data rates up to 10 Gbps per channel. The charge pumps are implemented to address the issue of voltage margin of the VCSEL driving stage in the applications under low temperature and harsh radiation environment. Test results indicate that cpVLAD is capable of driving VCSELs with forward voltages of up to 2.8 V using 1.2 V and 2.5 V power supplies with a power consumption of 94 mW/channel.
A system employing a desktop FADC has been developed to investigate the features of 8 inches Hamamatsu PMT. The system stands out for its high-speed and informative results as a consequence of adopting fast waveform sampling technology. Recording full waveforms allows us to perform digital signal processing, pulse shape analysis, and precision timing extraction. High precision after pulse time and charge distribution characteristics are presented in this manuscript. Other photomultipliers characteristics, such as dark rate and transit time spread, can also be obtained by exploiting waveform analysis using this system.
Belle II is a new-generation B-factory experiment, dedicated to exploring new physics beyond the standard model of elementary particles in the flavor sector. Belle~II started data-taking in April 2018, using a synchronous data acquisition (DAQ) system based on pipelined trigger flow control. The Belle II DAQ system is designed to handle a 30-kHz trigger rate with approximately 1% of dead time, under the assumption of a raw event size of 1 MB. The DAQ system is reliable, and the overall data-taking efficiency reached 84.2% during the run period of January 2020 to June 2020. The current readout system cannot be operated in the term of 10 years from the viewpoint of DAQ maintainability; meanwhile, the readout system is obstructing high-speed data transmission. A solution involving a PCI-express-based readout module with high data throughput of up to 100 Gb/s was adopted to upgrade the Belle II DAQ system. We particularly focused on the design of firmware and software based on this new generation of readout board, called PCIe40, with an Altera Arria 10 field-programmable gate array chip. Forty-eight GBT (GigaBit Transceiver) serial links, PCI-express hard IP-based DMA architecture, interface of timing and trigger distribution system, and slow control system were designed to integrate with the current Belle II DAQ system. This paper describes the performances accomplished during the data readout and slow control tests conducted using a test bench and a demonstration performed using on-site front-end electronics, specifically involving Belle II TOP and KLM sub-detectors.
The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micromegas detector of the ATLAS New Small Wheel (NSW) upgrade. The ART signals are generated by the front end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and do the hit-selection processing. Processed data from ART ASIC will be transmitted out of the NSW detector through GBTx serializer, VTTx optical transmitter module and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the functionality and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FMC based testing platform and special firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA develop kit, even without the other electronics of the NSW it can test all the functionality of the ADDC and also long term stability. This paper will introduce the design, testing procedure and results from the ADDC and the FMC testing platform.
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