No Arabic abstract
A PC based high speed silicon microstrip beam telescope consisting of several independent modules is presented. Every module contains an AC-coupled double sided silicon microstrip sensor and a complete set of analog and digital signal processing electronics. A digital bus connects the modules with the DAQ PC. A trigger logic unit coordinates the operation of all modules of the telescope. The system architecture allows easy integration of any kind of device under test into the data acquisition chain. Signal digitization, pedestal correction, hit detection and zero suppression are done by hardware inside the modules, so that the amount of data per event is reduced by a factor of 80 compared to conventional readout systems. In combination with a two level data acquisition scheme, this allows event rates up to 7.6 kHz. This is a factor of 40 faster than conventional VME based beam telescopes while comparable analog performance is maintained achieving signal to noise ratios of up to 70:1. The telescope has been tested in the SPS testbeam at CERN. It has been adopted as the reference instrument for testbeam studies for the ATLAS pixel detector development.
This paper describes the mechanical design, the readout chain, the production, testing and the installation of the Silicon Microstrip Tracker of the D0 experiment at the Fermilab Tevatron collider. In addition, description of the performance of the detector during the experiment data collection between 2001 and 2010 is provided.
The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 6*10^34 cm^-2 s^-1. A consequence of this increased luminosity is the expected radiation damage at 3000 fb^-1 after ten years of operation, requiring the tracking detectors to withstand fluences to over 1*10^16 1 MeV n_eq/cm^2 . In order to cope with the consequent increased readout rates, a complete re-design of the current ATLAS Inner Detector (ID) is being developed as the Inner Tracker (ITk). Two proposed detectors for the ATLAS strip tracker region of the ITk were characterized at the Diamond Light Source with a 3 um FWHM 15 keV micro focused X-ray beam. The devices under test were a 320 Um thick silicon stereo (Barrel) ATLAS12 strip mini sensor wire bonded to a 130 nm CMOS binary readout chip (ABC130) and a 320 Um thick full size radial (end-cap) strip sensor - utilizing bi-metal readout layers - wire bonded to 250 nm CMOS binary readout chips (ABCN-25). A resolution better than the inter strip pitch of the 74.5 um strips was achieved for both detectors. The effect of the p-stop diffusion layers between strips was investigated in detail for the wire bond pad regions. Inter strip charge collection measurements indicate that the effective width of the strip on the silicon sensors is determined by p-stop regions between the strips rather than the strip pitch.
EUDAQ is a generic data acquisition software developed for use in conjunction with common beam telescopes at charged particle beam lines. Providing high-precision reference tracks for performance studies of new sensors, beam telescopes are essential for the research and development towards future detectors for high-energy physics. As beam time is a highly limited resource, EUDAQ has been designed with reliability and ease-of-use in mind. It enables flexible integration of different independent devices under test via their specific data acquisition systems into a top-level framework. EUDAQ controls all components globally, handles the data flow centrally and synchronises and records the data streams. Over the past decade, EUDAQ has been deployed as part of a wide range of successful test beam campaigns and detector development applications.
When testing and calibrating particle detectors in a test beam, accurate tracking information independent of the detector being tested is extremely useful during the offline analysis of the data. A general-purpose Silicon Beam Tracker (SBT) was constructed with an active area of 32.0 x 32.0 mm2 to provide this capability for the beam calibration of the Cosmic Ray Energetics And Mass (CREAM) calorimeter. The tracker consists of two modules, each comprised of two orthogonal layers of 380 {mu}m thick silicon strip sensors. In one module each layer is a 64-channel AC-coupled single-sided silicon strip detector (SSD) with a 0.5 mm pitch. In the other, each layer is a 32-channel DC-coupled single-sided SSD with a 1.0 mm pitch. The signals from the 4 layers are read out using modified CREAM hodoscope front-end electronics with a USB 2.0 interface board to a Linux DAQ PC. In this paper, we present the construction of the SBT, along with its performance in radioactive source tests and in a CERN beam test in October 2006.
High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due the sensitivity of SRAM-based FPGA to radiation faults (single event upsets). However, the device tolerance to radiation environments can be achieved by adopting dedicated mitigation techniques such as information redundancy, hardware redundancy and configuration scrubbing. In this work, we discuss the design of a bi-directional serial link running at 6.25 Gbps based on a Xilinx Kintex-7 FPGA. The link is protected against single event upsets by means of all the above-mentioned methods. A self-synchronizing scrambler is used for DC-balance and data randomization, while the subsequent Reed-Solomon encoder/decoder detects and corrects bursts of errors in the transmitted data. The error correction capability of the line code is further increased by adopting the interleaving technique. Besides, in order to completely take advantage of available bandwidth and to cope with different rates of radiation-induced faults, the link can modulate the protection level of the Reed-Solomon code. The reliability of the link is also improved by means of modular redundancy on the frame alignment block. Besides, on the same FPGA, a scrubber repairs corrupted configuration frames in real-time. We present the test results carried out using the fault injection method. We show the performance of the link in terms of mean time between failures (MTBF) and fault tolerance to upsets.