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Register a new userRadiation resistant LGAD design
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Nicol\\`o Cartiglia
Publication date
2018
fields
Physics
and research's language is
English
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In this paper, we report on the radiation resistance of 50-micron thick LGAD detectors manufactured at the Fondazione Bruno Kessler employing several different doping combinations of the gain layer. LGAD detectors with gain layer doping of Boron, Boron low-diffusion, Gallium, Carbonated Boron and Carbonated Gallium have been designed and successfully produced. These sensors have been exposed to neutron fluences up to $phi_n sim 3 cdot 10^{16}; n/cm^2$ and to proton fluences up to $phi_p sim 9cdot10^{15}; p/cm^2$ to test their radiation resistance. The experimental results show that Gallium-doped LGADs are more heavily affected by initial acceptor removal than Boron-doped LGAD, while the presence of Carbon reduces initial acceptor removal both for Gallium and Boron doping. Boron low-diffusion shows a higher radiation resistance than that of standard Boron implant, indicating a dependence of the initial acceptor removal mechanism upon the implant width. This study also demonstrates that proton irradiation is at least twice more effective in producing initial acceptor removal, making proton irradiation far more damaging than neutron irradiation.
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The properties of 50 um thick Low Gain Avalanche Diode (LGAD) detectors manufactured by Hamamatsu photonics (HPK) and Fondazione Bruno Kessler (FBK) were tested before and after irradiation with 1 MeV neutrons. Their performance were measured in charge collection studies using b-particles from a 90Sr source and in capacitance-voltage scans (C-V) to determine the bias to deplete the gain layer. Carbon infusion to the gain layer of the sensors was tested by FBK in the UFSD3 production. HPK instead produced LGADs with a very thin, highly doped and deep multiplication layer. The sensors were exposed to a neutron fluence from 4e14 neq/cm2 to 4e15 neq/cm2. The collected charge and the timing resolution were measured as a function of bias voltage at -30C, furthermore the profile of the capacitance over voltage of the sensors was measured.
We study the radiation effects of the Low Gain Avalanche Detector (LGAD) sensors developed by the Institute of High Energy Physics (IHEP) and the Novel Device Laboratory (NDL) of Beijing Normal University in China. These new sensors have been irradiated at the China Institute of Atomic Energy (CIAE) using 100 MeV proton beam with five different fluences from 7$times10^{14}$ $n_{eq}/cm^2$ up to 4.5$times10^{15}$ $n_{eq}/cm^2$. The result shows the effective doping concentration in the gain layer decreases with the increase of irradiation fluence, as expected by the acceptor removal mechanism. By comparing data and model gives the acceptor removal coefficient $c_{A}$ = $(6.07pm0.70)times10^{-16}~cm^2$, which indicates the NDL sensor has fairly good radiation resistance.
High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due the sensitivity of SRAM-based FPGA to radiation faults (single event upsets). However, the device tolerance to radiation environments can be achieved by adopting dedicated mitigation techniques such as information redundancy, hardware redundancy and configuration scrubbing. In this work, we discuss the design of a bi-directional serial link running at 6.25 Gbps based on a Xilinx Kintex-7 FPGA. The link is protected against single event upsets by means of all the above-mentioned methods. A self-synchronizing scrambler is used for DC-balance and data randomization, while the subsequent Reed-Solomon encoder/decoder detects and corrects bursts of errors in the transmitted data. The error correction capability of the line code is further increased by adopting the interleaving technique. Besides, in order to completely take advantage of available bandwidth and to cope with different rates of radiation-induced faults, the link can modulate the protection level of the Reed-Solomon code. The reliability of the link is also improved by means of modular redundancy on the frame alignment block. Besides, on the same FPGA, a scrubber repairs corrupted configuration frames in real-time. We present the test results carried out using the fault injection method. We show the performance of the link in terms of mean time between failures (MTBF) and fault tolerance to upsets.
The High-Granularity Timing Detector is a detector proposed for the ATLAS Phase II upgrade. The detector, based on the Low-Gain Avalanche Detector (LGAD) technology will cover the pseudo-rapidity region of $2.4<|eta|<4.0$ with two end caps on each side and a total area of 6.4 $m^2$. The timing performance can be improved by implanting an internal gain layer that can produce signal with a fast rising edge, which improve significantly the signal-to-noise ratio. The required average timing resolution per track for a minimum-ionising particle is 30 ps at the start and 50 ps at the end of the HL-LHC operation. This is achieved with several layers of LGAD. The innermost region of the detector would accumulate a 1 MeV-neutron equivalent fluence up to $2.5 times 10^{15} cm^{-2}$ before being replaced during the scheduled shutdowns. The addition of this new detector is expected to play an important role in the mitigation of high pile-up at the HL-LHC. The layout and performance of the vario
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.
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