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Register a new userTunable Schottky barrier and high responsivity in graphene/Si-nanotip optoelectronic device
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Added by
Antonio Di Bartolomeo
Publication date
2016
fields
Physics
and research's language is
English
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We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 A/W for white LED light at 3 mW/cm2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications.
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We show the operation of a Cu/Al_2O_3/Cu/n-Si hot-electron transistor for the straightforward determination of a metal/semiconductor energy barrier height even at temperatures below carrier-freeze out in the semiconductor. The hot-electron spectroscopy measurements return a fairly temperature independent value for the Cu/n-Si barrier of 0.66 $pm$ 0.04 eV at temperatures below 180 K, in substantial accordance with mainstream methods based on complex fittings of either current-voltage (I-V) and capacitance-voltage (C-V) measurements. The Cu/n-Si hot-electron transistors exhibit an OFF current of ~2 * 10^-13 A, an ON/OFF ratio of ~10^5 and an equivalent subtreshold swing of ~96 mV/dec at low temperatures, which are suitable values for potential high frequency devices.
Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.
A scheme is proposed to electrically measure the spin-momentum coupling in the topological insulator surface state by injection of spin polarized electrons from silicon. As a first approach, devices were fabricated consisting of thin (<100nm) exfoliated crystals of Bi2Se3 on n-type silicon with independent electrical contacts to silicon and Bi2Se3. Analysis of the temperature dependence of thermionic emission in reverse bias indicates a barrier height of 0.34 eV at the Si-Bi2Se3 interface. This robust Schottky barrier opens the possibility of novel device designs based on sub-band gap internal photoemission from Bi2Se3 into Si.
Schottky barrier field-effect transistors (SBFETs) based on few and mono layer phosphorene are simulated by the non-equilibrium Greens function formalism. It is shown that scaling down the gate oxide thickness results in pronounced ambipolar I-V characteristics and significant increase of the minimal leakage current. The problem of leakage is especially severe when the gate insulator is thin and the number of layer is large, but can be effectively suppressed by reducing phosphorene to mono or bilayer. Different from two-dimensional graphene and layered dichalcogenide materials, both the ON-current of the phosphorene SBFETs and the metal-semiconductor contact resistance between metal and phosphorene strongly depend on the transport crystalline direction.
Hybrid graphene photoconductor/phototransistor has achieved giant photoresponsivity, but its response speed dramatically degrades as the expense due to the long lifetime of trapped interfacial carriers. In this work, by intercalating a large-area atomically thin MoS2 film into a hybrid graphene photoconductor, we have developed a prototype tunneling photoconductor, which exhibits a record-fast response (rising time ~17 ns) and a high responsivity (~$3times10^4$ A/W at 635 nm and 16.8 nW illumination) across the broad spectral range. We demonstrate that the photo-excited carriers generated in silicon are transferred into graphene through a tunneling process rather than carrier drift. The atomically thin MoS2 film not only serves as tunneling layer but also passivates surface states, which in combination delivers a superior response speed (~3 order of magnitude improved than a device without MoS2 layer), while the responsivity remains high. This intriguing tunneling photoconductor integrates both fast response and high responsivity and thus has significant potential in practical applications of optoelectronic devices.
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