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Register a new userReliable determination of the Cu/n-Si Schottky barrier height by using in-device hot-electron spectroscopy
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We show the operation of a Cu/Al_2O_3/Cu/n-Si hot-electron transistor for the straightforward determination of a metal/semiconductor energy barrier height even at temperatures below carrier-freeze out in the semiconductor. The hot-electron spectroscopy measurements return a fairly temperature independent value for the Cu/n-Si barrier of 0.66 $pm$ 0.04 eV at temperatures below 180 K, in substantial accordance with mainstream methods based on complex fittings of either current-voltage (I-V) and capacitance-voltage (C-V) measurements. The Cu/n-Si hot-electron transistors exhibit an OFF current of ~2 * 10^-13 A, an ON/OFF ratio of ~10^5 and an equivalent subtreshold swing of ~96 mV/dec at low temperatures, which are suitable values for potential high frequency devices.
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We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 A/W for white LED light at 3 mW/cm2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications.
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Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.
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