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تسجيل مستخدم جديدTriple Patterning Lithography (TPL) Layout Decomposition using End-Cutting
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Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end-cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the conflict number and the stitch number.
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Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. Conventional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently, as an alternative process, triple
patterning lithography with end cutting (LELE-EC) was proposed to overcome the limitations of LELELE manufacturing. In LELE-EC process the first two masks are LELE type double patterning, while the third mask is used to generate the end-cuts. Although the layout decomposition problem for LELELE has been well-studied in the literature, only few attempts have been made to address the LELE-EC layout decomposition problem. In this paper we propose the comprehensive study for LELE-EC layout decomposition. Conflict graph and end-cut graph are constructed to extract all the geometrical relationships of both input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the conflict number and the stitch number. The experimental results demonstrate the effectiveness of the proposed algorithms.
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