اشترك بالحزمة الذهبية واحصل على وصول غير محدود شمرا أكاديميا
تسجيل مستخدم جديدLithography Hotspot Detection and Mitigation in Nanometer VLSI
119
0
0.0
(
0
)
اسأل ChatGPT حول البحث
ﻻ يوجد ملخص باللغة العربية
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.
قيم البحث
اقرأ أيضاً
As technology scaling is approaching the physical limit, lithography hotspot detection has become an essential task in design for manufacturability. While the deployment of pattern matching or machine learning in hotspot detection can help save signi
ficant simulation time, such methods typically demand for non-trivial quality data to build the model, which most design houses are short of. Moreover, the design houses are also unwilling to directly share such data with the other houses to build a unified model, which can be ineffective for the design house with unique design patterns due to data insufficiency. On the other hand, with data homogeneity in each design house, the locally trained models can be easily over-fitted, losing generalization ability and robustness. In this paper, we propose a heterogeneous federated learning framework for lithography hotspot detection that can address the aforementioned issues. On one hand, the framework can build a more robust centralized global sub-model through heterogeneous knowledge sharing while keeping local data private. On the other hand, the global sub-model can be combined with a local sub-model to better adapt to local data heterogeneity. The experimental results show that the proposed framework can overcome the challenge of non-independent and identically distributed (non-IID) data and heterogeneous communication to achieve very high performance in comparison to other state-of-the-art methods while guaranteeing a good convergence rate in various scenarios.
We propose an approach for super-resolution optical lithography which is based on the inverse of magnetic resonance imaging (MRI). The technique uses atomic coherence in an ensemble of spin systems whose final state population can be optically detect
ed. In principle, our method is capable of producing arbitrary one and two dimensional high-resolution patterns with high contrast.
Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard cells are replaced by synchoros large grain VLSI design objects called SiLago blocks. This new design style enables end-to-end automation of large
scale designs by abutting the SiLago blocks to eliminate logic and physical synthesis for the end-users. A key problem in this automation process is the generation of regional clock tree. Synchoros design style requires that the clock tree should emerge by abutting its fragments. The clock tree fragments are absorbed in the SiLago blocks as a one-time engineering effort. The clock tree should not be ad-hoc, but a structured and predictable design whose cost metrics are known. Here, we present a new clock tree design that is compatible with the synchoros design style. The proposed design has been verified with static timing analysis and compared against functionally equivalent clock tree synthesised by the commercial EDA tools. The scheme is scalable and, in principle, can generate arbitrarily complex designs. In this paper, we show as a proof of concept that a regional clock tree can be created by abutment. We prove that with the help of the generated clock tree, it is possible to generate valid VLSI designs from 0.5 to ~2 million gates. The resulting generated designs do not need a separate regional clock tree synthesis. More critically, the synthesised design is correct by construction and requires no further verification. In contrast, the state-of-the-art hierarchical synthesis flow requires synthesis of the regional clock tree. Additionally, the conventional clock tree and its design needs a verification step because it lacks predictability. The results also demonstrate that the capacitance, slew and the ability to balance skew of the clock tree created by abutment is comparable to the one generated by commercial EDA tools.
As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within
standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition.
Layout fracturing is a fundamental step in mask data preparation and e-beam lithography (EBL) writing. To increase EBL throughput, recently a new L-shape writing strategy is proposed, which calls for new L-shape fracturing, versus the conventional re
ctangular fracturing. Meanwhile, during layout fracturing, one must minimize very small/narrow features, also called slivers, due to manufacturability concern. This paper addresses this new research problem of how to perform L-shaped fracturing with sliver minimization. We propose two novel algorithms. The first one, rectangular merging (RM), starts from a set of rectangular fractures and merges them optimally to form L-shape fracturing. The second algorithm, direct L-shape fracturing (DLF), directly and effectively fractures the input layouts into L-shapes with sliver minimization. The experimental results show that our algorithms are very effective.
سجل دخول لتتمكن من نشر تعليقات
التعليقات
جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
