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We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $mu$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180~nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695$pm$71~e$^-$ (rms) with a detector capacitance of 300~pF. The dynamic range was measured to be 20--100~fC in the low-gain mode and 200--1600~fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout channels, and
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO
We have developed a dedicated front-end-electronics board for a high-pressure xenon gas time projection chamber for a neutrinoless double-beta decay search. The ionization signal is readout by detecting electroluminescence photons with SiPMs. The boa
Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) det
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm