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Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) detectors for gamma ray spectroscopy is presented. Corresponding to each ionizing event in the detector, the ASIC measures the amplitude and timing at the anode, the cathode and four pad sense electrodes associated with each sensor in a detector array. The ASIC is comprised of 52 channels of which there are 4 cathode channels and 48 channels which can be configured as either anode channels with a baseline of 250 mV or pad sense channels to process induced signals with a baseline of 1.2 V. With a static power dissipation of 3 mW, each channel performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. The overall channel linearity was better than $pm$ 1 % with timing resolution down to 700 ps for charges greater than 8 fC in the 3 MeV range. With a 4 x 4 array of 6 mm x 6 mm x 20 mm virtual Frisch-grid bar sensors connected and biased, an electronic resolution of $approx$ 270 rms $e^{-}$ for charges up to 100 fC in the 3.2 MeV range was measured. Spectral measurements obtained with the 3D correction technique demonstrated resolutions of 1.8 % FWHM at 238 keV and 0.9 % FWHM at 662 keV.
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $mu$-TPCs for directional dark matter searches. Low-noise performance and wid
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Aval