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This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent $V_{TH}$ controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.
Extensive electrical characterization of ring oscillators (ROs) made in high-$kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($tau_P$
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental devic
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at
The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state
We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information - so-called