اشترك بالحزمة الذهبية واحصل على وصول غير محدود شمرا أكاديميا
تسجيل مستخدم جديدAn auto-scaling wide dynamic range current to frequency converter for real-time monitoring of signals in neuromorphic systems
259
0
0.0
(
0
)
اسأل ChatGPT حول البحث
ﻻ يوجد ملخص باللغة العربية
Neuromorphic systems typically employ current-mode circuits that model neural dynamics and produce output currents that range from few pico-Amperes to hundreds of micro-Amperes. On-line real-time monitoring of the signals produced by these circuits is crucial, for prototyping and debugging purposes, as well as for analyzing and understanding the network dynamics and computational properties. To this end, we propose a compact on-chip auto-scaling Current to Frequency Converter (CFC) for real-time monitoring of analog currents in mixed-signal/analog neuromorphic electronic systems. The proposed CFC is a self-timed asynchronous circuit that has a wide dynamic input range of up to 6 decades, ranging from pico-Amps to micro-Amps, with high current measurement sensitivity. To produce a linear output frequency response, while properly covering the wide dynamic input range, the circuit automatically detects the scale of the input current and adjusts the scale of its output firing rate accordingly. Here we describe the proposed circuit and present experimental results measured from multiple instances of the circuit, implemented using a standard 180 nm CMOS process, and interfaced to silicon neuron and synapse circuits for real-time current monitoring. We demonstrate how the circuit is suitable for measuring neural dynamics by showing the converted response properties of the chip silicon neurons and synapses as they are stimulated by input spikes.
قيم البحث
اقرأ أيضاً
High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in Time Interlea
ved Analog-to-Digital Converter (TIADC) systems. We focus on correction with wide-band input signal, which means that we can correct the mismatch errors for any frequency point in a broad band with only one set of filter coefficients. Studies were also made to show how to apply the correction algorithm beyond the base band, i.e. other Nyquist zones in the under-sampling situation. Structure of the correction algorithm is presented in this paper, as well as simulation results. To evaluate the correction performance, we actually conducted a series of tests with two TIADC systems. The results indicate that the performance of both two TIADC systems can be greatly improved by correction, and the Effective Number Of Bits (ENOB) is successfully improved to be better than 9.5 bits and 5.5 bits for an input signal up to the bandwidth (-3dB) range in the 1.6-Gsps 14-bit and the 10-Gsps 8-bit TIADC systems, respectively. Tests were also conducted for input signal frequencies in the second Nyquist zone, which shows that the correction algorithms also work well as expected.
As processes continue to scale aggressively, the design of deep sub-micron, mixed-signal design is becoming more and more challenging. In this paper we present an analysis of scaling multi-core mixed-signal neuromorphic processors to advanced 28 nm F
D-SOI nodes. We address analog design issues which arise from the use of advanced process, including the problem of large leakage currents and device mismatch, and asynchronous digital design issues. We present the outcome of Monte Carlo Analysis and circuit simulations of neuromorphic sub threshold analog/digital neuron circuits which reproduce biologically plausible responses. We describe the AER used to implement PCHB based asynchronous QDI routing processes in multi-core neuromorphic architectures and validate their operation via circuit simulation results. Finally we describe the implementation of custom 28 nm CAM based memory resources utilized in these multi-core neuromorphic processor and discuss the possibility of increasing density by using advanced RRAM devices integrated in the 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) process.
This work presents the design and analysis of a mixed-signal neuron (MS-N) for convolutional neural networks (CNN) and compares its performance with a digital neuron (Dig-N) in terms of operating frequency, power and noise. The circuit-level implemen
tation of the MS-N in 65 nm CMOS technology exhibits 2-3 orders of magnitude better energy-efficiency over Dig-N for neuromorphic computing applications - especially at low frequencies due to the high leakage currents from many transistors in Dig-N. The inherent error-resiliency of CNN is exploited to handle the thermal and flicker noise of MS-N. A system-level analysis using a cohesive circuit-algorithmic framework on MNIST and CIFAR-10 datasets demonstrate an increase of 3% in worst-case classification error for MNIST when the integrated noise power in the bandwidth is ~ 1 {mu}V2.
In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processin
g, and detecting High Frequency Oscillations (HFO), which are biomarkers for the epileptogenic zone. The device was fabricated using a standard 0.18$mu$m CMOS technology node and has a total area of 99mm$^{2}$. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3$mu$W. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing neuromorphic intelligence to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.
Several analog and digital brain-inspired electronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these architectures are useful for exploring the computational properties of large-
scale models of the nervous system, the challenge of building low-power compact physical artifacts that can behave intelligently in the real-world and exhibit cognitive abilities still remains open. In this paper we propose a set of neuromorphic engineering solutions to address this challenge. In particular, we review neuromorphic circuits for emulating neural and synaptic dynamics in real-time and discuss the role of biophysically realistic temporal dynamics in hardware neural processing architectures; we review the challenges of realizing spike-based plasticity mechanisms in real physical systems and present examples of analog electronic circuits that implement them; we describe the computational properties of recurrent neural networks and show how neuromorphic Winner-Take-All circuits can implement working-memory and decision-making mechanisms. We validate the neuromorphic approach proposed with experimental results obtained from our own circuits and systems, and argue how the circuits and networks presented in this work represent a useful set of components for efficiently and elegantly implementing neuromorphic cognition.
سجل دخول لتتمكن من نشر تعليقات
التعليقات
جاري جلب التعليقات
سجل دخول لتتمكن من متابعة معايير البحث التي قمت باختيارها
