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تسجيل مستخدم جديدCharacterization of a depleted monolithic pixel sensors in 150 nm CMOS technology for the ATLAS Inner Tracker upgrade
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Francisco Jose Iguaz Gutierrez Dr.
تاريخ النشر
2018
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فيزياء
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English
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This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower material budget compared to presently used hybrid designs. In this work, the chip architecture will be described followed by the characterization of the different pre-amplifier and discriminator flavors with an external injection signal and an iron source (5.9,keV x-rays).
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This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a
downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.
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