We extend the circuit model of quantum comuptation so that the wiring between gates is soft-coded within registers inside the gates. The addresses in these registers can be manipulated and put into superpositions. This aims at capturing indefinite ca
usal orders, as well as making their geometrical layout explicit. We show how to implement the quantum switch and the polarizing beam splitter within our model. One difficulty is that the names used as addresses should not matter beyond the wiring they describe, i.e. the evolution should commute with renamings. Yet, the evolution may act nontrivially on these names. Our main technical contribution is a full characterization of such nameblind matrices.
We present a generalization of the binary paint shop problem (BPSP) to tackle an automotive industry application, the multi-car paint shop (MCPS) problem. The objective of the optimization is to minimize the number of color switches between cars in a
paint shop queue during manufacturing, a known NP-hard problem. We distinguish between different sub-classes of paint shop problems, and show how to formulate the basic MCPS problem as an Ising model. The problem instances used in this study are generated using real-world data from a factory in Wolfsburg, Germany. We compare the performance of the D-Wave 2000Q and Advantage quantum processors to other classical solvers and a hybrid quantum-classical algorithm offered by D-Wave Systems. We observe that the quantum processors are well-suited for smaller problems, and the hybrid algorithm for intermediate sizes. However, we find that the performance of these algorithms quickly approaches that of a simple greedy algorithm in the large size limit.
Reconfigurable Intelligent Surfaces (RISs), comprising large numbers of low-cost and passive metamaterials with tunable reflection properties, have been recently proposed as an enabler for programmable radio propagation environments. However, the rol
e of the channel conditions near the RISs on their optimizability has not been analyzed adequately. In this paper, we present an asymptotic closed-form expression for the mutual information of a multi-antenna transmitter-receiver pair in the presence of multiple RISs, in the large-antenna limit, using the random matrix and replica theories. Under mild assumptions, asymptotic expressions for the eigenvalues and the eigenvectors of the channel covariance matrices are derived. We find that, when the channel close to an RIS is correlated, for instance due to small angle spread, the communication link benefits significantly from the RIS optimization, resulting in gains that are surprisingly higher than the nearly uncorrelated case. Furthermore, when the desired reflection from the RIS departs significantly from geometrical optics, the surface can be optimized to provide robust communication links. Building on the properties of the eigenvectors of the covariance matrices, we are able to find the optimal response of the RISs in closed form, bypassing the need for brute-force optimization.
Randomized benchmarking (RB) is a widely used method for estimating the average fidelity of gates implemented on a quantum computing device. The stochastic error of the average gate fidelity estimated by RB depends on the sampling strategy (i.e., how
to sample sequences to be run in the protocol). The sampling strategy is determined by a set of configurable parameters (an RB configuration) that includes Clifford lengths (a list of the number of independent Clifford gates in a sequence) and the number of sequences for each Clifford length. The RB configuration is often chosen heuristically and there has been little research on its best configuration. Therefore, we propose a method for fully optimizing an RB configuration so that the confidence interval of the estimated fidelity is minimized while not increasing the total execution time of sequences. By experiments on real devices, we demonstrate the efficacy of the optimization method against heuristic selection in reducing the variance of the estimated fidelity.
In this work we propose an effective preconditioning technique to accelerate the steady-state simulation of large-scale memristor crossbar arrays (MCAs). We exploit the structural regularity of MCAs to develop a specially-crafted preconditioner that
can be efficiently evaluated utilizing tensor products and block matrix inversion. Numerical experiments demonstrate the efficacy of the proposed technique compared to mainstream preconditioners.
Highly sensitive photodetectors with single photon level detection is one of the key components to a range of emerging technologies, in particular the ever-growing field of optical communication, remote sensing, and quantum computing. Currently, most
of the single-photon detection technologies require external biasing at high voltages and/or cooling to low temperatures, posing great limitations for wider applications. Here, we demonstrate InP nanowire array photodetectors that can achieve single-photon level light detection at room temperature without an external bias. We use top-down etched, heavily doped p-type InP nanowires and n-type AZO/ZnO carrier selective contact to form a radial p-n junction with a built-in electric field exceeding 3x10^5 V/cm at 0 V. The device exhibits broadband light sensitivity and can distinguish a single photon per pulse from the dark noise at 0 V, enabled by its design to realize near-ideal broadband absorption, extremely low dark current, and highly efficient charge carrier separation. Meanwhile, the bandwidth of the device reaches above 600 MHz with a timing jitter of 538 ps. The proposed device design provides a new pathway towards low-cost, high-sensitivity, self-powered photodetectors for numerous future applications.
We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysi
s to evaluate system-level performance of new CMOS technologies. As the impact of parasitic resistances and capacitances continues to increase with dimensional downscaling, component-level optimization alone becomes insufficient, calling for a holistic assessment and optimization methodology across the boundaries between devices, interconnects, circuits, and systems. The physical implementation flow in DISPEL enables realistic analysis of complex wires and vias in VLSI systems and their impact on the chip power, speed, and area, which simple circuit simulations cannot capture. To demonstrate the use of DISPEL, a 32-bit commercial processor core is implemented using theoretical n-type MoS2 and p-type Black Phosphorous (BP) planar FETs at a projected 5-nm node, and the performance is benchmarked against Si FinFETs. While the superior gate control of the MoS2/BP FETs can theoretically provide 51% reduction in the iso-frequency energy consumption, the actual performance can be greatly limited by the source/drain contact resistances. With the large amount of data generated by DISPEL, a neural-network is trained to predict the key performance metrics of the 32-bit processor core using the characteristics of transistors and interconnects as the input features without the need to go through the time-consuming physical implementation flow. The machine learning algorithms show great potentials as a means for evaluation and optimization of new CMOS technologies and identifying the most significant technology design parameters.
Digital accelerators in the latest generation of CMOS processes support multiply and accumulate (MAC) operations at energy efficiencies spanning 10-to-100~fJ/Op. But the operating speed for such MAC operations are often limited to a few hundreds of M
Hz. Optical or optoelectronic MAC operations on todays SOI-based silicon photonic integrated circuit platforms can be realized at a speed of tens of GHz, leading to much lower latency and higher throughput. In this paper, we study the energy efficiency of integrated silicon photonic MAC circuits based on Mach-Zehnder modulators and microring resonators. We describe the bounds on energy efficiency and scaling limits for N x N optical networks with todays technology, based on the optical and electrical link budget. We also describe research directions that can overcome the current limitations. The next generation of silicon photonics, which we term Silicon Photonics 2.0, promises many exciting opportunities to enable the next frontier in optical computing and communication.
Before quantum error correction (QEC) is achieved, quantum computers focus on noisy intermediate-scale quantum (NISQ) applications. Compared to the well-known quantum algorithms requiring QEC, like Shors or Grovers algorithm, NISQ applications have d
ifferent structures and properties to exploit in compilation. A key step in compilation is mapping the qubits in the program to physical qubits on a given quantum computer, which has been shown to be an NP-hard problem. In this paper, we present OLSQ-GA, an optimal qubit mapper with a key feature of simultaneous SWAP gate absorption during qubit mapping, which we show to be a very effective optimization technique for NISQ applications. For the class of quantum approximate optimization algorithm (QAOA), an important NISQ application, OLSQ-GA reduces depth by up to 50.0% and SWAP count by 100% compared to other state-of-the-art methods, which translates to 55.9% fidelity improvement. The solution optimality of OLSQ-GA is achieved by the exact SMT formulation. For better scalability, we augment our approach with additional constraints in the form of initial mapping or alternating matching, which speeds up OLSQ-GA by up to 272X with no or little loss of optimality.
Real stabilizer operators, which are also known as real Clifford operators, are generated, through composition and tensor product, by the Hadamard gate, the Pauli Z gate, and the controlled-Z gate. We introduce a normal form for real stabilizer circu
its and show that every real stabilizer operator admits a unique normal form. Moreover, we give a finite set of relations that suffice to rewrite any real stabilizer circuit to its normal form.
