The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphe
ne nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.
The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si
-face epitaxial graphene used in the prior high frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high {kappa} dielectric T-gate and self-aligned contacts, further contributed to the record-breaking fmax.
Graphene is generally considered to be a strong candidate to succeed silicon as an electronic material. However, to date, it actually has not yet demonstrated capabilities that exceed standard semiconducting materials. Currently demonstrated viable g
raphene devices are essentially limited to micron size ultrahigh frequency analog field effect transistors and quantum Hall effect devices for metrology. Nanoscopically patterned graphene tends to have disordered edges that severely reduce mobilities thereby obviating its advantage over other materials. Here we show that graphene grown on structured silicon carbide surfaces overcomes the edge roughness and promises to provide an inroad into nanoscale patterning of graphene. We show that high quality ribbons and rings can be made using this technique. We also report on progress towards high mobility graphene monolayers on silicon carbide for device applications.
After the pioneering investigations into graphene-based electronics at Georgia Tech (GT), great strides have been made developing epitaxial graphene on silicon carbide (EG) as a new electronic material. EG has not only demonstrated its potential for
large scale applications, it also has become an invaluable material for fundamental two-dimensional electron gas physics showing that only EG is on route to define future graphene science. It was long known that graphene mono and multilayers grow on SiC crystals at high temperatures in ultra-high vacuum. At these temperatures, silicon sublimes from the surface and the carbon rich surface layer transforms to graphene. However the quality of the graphene produced in ultrahigh vacuum is poor due to the high sublimation rates at relatively low temperatures. The GT team developed growth methods involving encapsulating the SiC crystals in graphite enclosures, thereby sequestering the evaporated silicon and bringing growth process closer to equilibrium. In this confinement controlled sublimation (CCS) process, very high quality graphene is grown on both polar faces of the SiC crystals. Since 2003, over 50 publications used CCS grown graphene, where it is known as the furnace grown graphene. Graphene multilayers grown on the carbon-terminated face of SiC, using the CCS method, were shown to consist of decoupled high mobility graphene layers. The CCS method is now applied on structured silicon carbide surfaces to produce high mobility nano-patterned graphene structures thereby demonstrating that EG is a viable contender for next-generation electronics. Here we present the CCS method and demonstrate several of epitaxial graphenes outstanding properties and applications.
Since its inception in 2001, the science and technology of epitaxial graphene on hexagonal silicon carbide has matured into a major international effort and is poised to become the first carbon electronics platform. A historical perspective is presen
ted and the unique electronic properties of single and multilayered epitaxial graphenes on electronics grade silicon carbide are reviewed. Early results on transport and the field effect in Si-face grown graphene monolayers provided proof-of-principle demonstrations. Besides monolayer epitaxial graphene, attention is given to C-face grown multilayer graphene, which consists of electronically decoupled graphene sheets. Production, structure, and electronic structure are reviewed. The electronic properties, interrogated using a wide variety of surface, electrical and optical probes, are discussed. An overview is given of recent developments of several device prototypes including resistance standards based on epitaxial graphene quantum Hall devices and new ultrahigh frequency analog epitaxial graphene amplifiers.
Three types of first generation epitaxial graphene field effect transistors (FET) are presented and their relative merits are discussed. Graphene is epitaxially grown on both the carbon and silicon faces of hexagonal silicon carbide and patterned wit
h electron beam lithography. The channels have a Hall bar geometry to facilitate magnetoresistance measurements. FETs patterned on the Si-face exhibit off-to-on channel resistance ratios that exceed 30. C-face FETs have lower off-to-on resistance ratios, but their mobilities (up to 5000 cm2/Vs) are much larger than that for Si-face transistors. Initial investigations into all-graphene side gate FET structures are promising.
This paper describes the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material. In the past decade research has identified carbon-based electronics as a possible alternative to silic
on-based electronics. This enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic carbon, can overcome some of these problems and therefore is a promising new electronic material. Although graphene devices have been built before, in this work we provide the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods. Graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micron-scale devices have negligible band gaps and therefore large leakage currents.
