A new Room Temperature (RT) 0-level vacuum package is demonstrated in this work, using amorphous silicon (aSi) as sacrificial layer and SiO2 as structural layer. The process is compatible with most of MEMS resonators and Resonant Suspended-Gate MOSFE
T [1] fabrication processes. This paper presents a study on the influence of releasing hole dimensions on the releasing time and hole clogging. It discusses mass production compatibility in terms of packaging stress during back-end plastic injection process. The packaging is done at room temperature making it fully compatible with IC-processed wafers and avoiding any subsequent degradation of the active devices.
A simple and fast process for micro-electromechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented in this paper. Thin SOI wafers are important for advanced CMOS technology and thus are evaluated as resonator subst
rates for future co-integration with CMOS circuitry on a single chip. As the transduction capacitance scales with the resonator thickness, it is important to fabricate deep sub-micron trenches in order to achieve a good capacitive coupling. Through the combination of conventional UV-lithography and focused ion beam (FIB) milling the process needs only two lithography steps, enabling therefore a way for fast prototyping of MEM-resonators. Different FIB parameters and etching parameters are compared in this paper and their effect on the process are reported.
