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Register a new userFPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics
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We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.
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The Compressed Baryonic Matter~(CBM) experiment in the upcoming Facility for Antiproton and Ion Research~(FAIR), designed to take data in nuclear collisions at very high interaction rates of up to 10 MHz, will employ a free-streaming data acquisition with self-triggered readout electronics, without any hardware trigger. A simulation framework with a realistic digitization of the detectors in the muon chamber (MuCh) subsystem in CBM has been developed to provide a realistic simulation of the time-stamped data stream. In this article, we describe the implementation of the free-streaming detector simulation and the basic data related effects on the detector with respect to the interaction rate.
The Trigger Data Serializer (TDS) is a custom ASIC designed for the upgrade of the innermost station of the endcap ATLAS Muon Spectrometer. It is a mixed-signal chip with two working modes that can handle up to 128 detector channels. A total of 6,000 TDS ASICs have been produced for detector operation. This paper discusses a custom automatic test platform we developed to provide quality control of the TDS ASICs. We introduce the design, test procedures, and results obtained from this TDS testing platform.
Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and measurements validates the ASIC latency characterization.
A full-size prototype of a Micromegas precision tracking chamber for the upgrade of the ATLAS detector at the LHC Collider has been built between October 2015 and April 2016. This paper describes in detail the procedures used in constructing the single modules of the chamber in various INFN laboratories and the final assembly at the Laboratori Nazionali di Frascati (LNF). Results of the chamber exposure to the CERN SPS/H8 beam line in June 2016 are also presented. The performances achieved in the construction and the results of the test beam are compared with the requirements, which are imposed by the severe environment during the data-taking of the LHC foreseen for the next years.
The High-Luminosity LHC (HL-LHC) will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first-level triggers are essential for the physics programme of the ATLAS experiment at HL-LHC, where the instantaneous luminosity will exceed the instantaneous LHC Run 1 luminosity by about an order of magnitude. The ATLAS first-level muon trigger rate is dominated by low momentum muons, which are accepted because of the moderate momentum resolution of the RPC and TGC trigger chambers. This limitation can be overcome by exploiting the data of the precision Muon Drift-Tube (MDT) chambers in the first-level trigger decision. This requires continuous fast transfer of the MDT hits to the off-detector trigger logic and fast track reconstruction algorithms. The reduction of the muon trigger rate achievable with the proposed new trigger concept, the performance of a novel fast track reconstruction algorithm, and the first hardware demonstration of the scheme with muon testbeam data taken at the CERN Gamma Irradiation Facility are discussed.
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