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Register a new userMass Production of a Trigger Data Serializer ASIC for the Upgrade of the Muon Spectrometer at the ATLAS Experiment
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The Trigger Data Serializer (TDS) is a custom ASIC designed for the upgrade of the innermost station of the endcap ATLAS Muon Spectrometer. It is a mixed-signal chip with two working modes that can handle up to 128 detector channels. A total of 6,000 TDS ASICs have been produced for detector operation. This paper discusses a custom automatic test platform we developed to provide quality control of the TDS ASICs. We introduce the design, test procedures, and results obtained from this TDS testing platform.
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A full-size prototype of a Micromegas precision tracking chamber for the upgrade of the ATLAS detector at the LHC Collider has been built between October 2015 and April 2016. This paper describes in detail the procedures used in constructing the single modules of the chamber in various INFN laboratories and the final assembly at the Laboratori Nazionali di Frascati (LNF). Results of the chamber exposure to the CERN SPS/H8 beam line in June 2016 are also presented. The performances achieved in the construction and the results of the test beam are compared with the requirements, which are imposed by the severe environment during the data-taking of the LHC foreseen for the next years.
The steadily increasing luminosity of the LHC requires an upgrade with high-rate and high-resolution detector technology for the inner end cap of the ATLAS muon spectrometer: the New Small Wheels (NSW). In order to achieve the goal of precision tracking at a hit rate of about 15 kHz/cm$^2$ at the inner radius of the NSW, large area Micromegas quadruplets with 100,microns spatial resolution per plane have been produced. % IRFU, from the CEA research center of Saclay, is responsible for the production and validation of LM1 Micromegas modules. The construction, production, qualification and validation of the largest Micromegas detectors ever built are reported here. Performance results under cosmic muon characterisation will also be discussed.
In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-um Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.
We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.
A very compact architecture has been developed for the first level Muon Trigger of the LHCb experiment that processes 40 millions of proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 microseconds latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.
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