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Register a new userThe Latency Validation of the Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade
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Two optical data link data transmission Application Specific Integrated Circuits (ASICs), the baseline and its backup, have been designed for the ATLAS Liquid Argon (LAr) Calorimeter Phase-I trigger upgrade. The latency of each ASIC and that of its corresponding receiver implemented in a back-end Field-Programmable Gate Array (FPGA) are critical specifications. In this paper, we present the latency measurements and simulation of two ASICs. The measurement results indicate that both ASICs achieve their design goals and meet the latency specifications. The consistency between the simulation and measurements validates the ASIC latency characterization.
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A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.
We present the procedures and results of the quality control tests for the front-end optical link components in the ATLAS Liquid Argon Calorimeter Phase-1 upgrade. The components include a Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld, custom optical transmitter/transceiver modules MTx/MTRx, and a transmitter ASIC LOCx2. LOCld, MTx, and LOCx2 each contain two channels with the same structure, while MTRx has a transmitter channel and a receiver channel. Each channel is tested at 5.12 Gbps. A total of 5341 LOCld chips, 3275 MTx modules, 797 MTRx modules, and 3198 LOCx2 chips are qualified. The yields are 73.9%, 98.0%, 98.4%, and 61.9% for LOCld, LOCx2, MTx, and MTRx, respectively.
In this paper, we present the design and test results of LOCx2, a transmitter ASIC for the ATLAS Liquid Argon Calorimeter trigger upgrade. LOCx2 consists of two channels and each channel encodes ADC data with an overhead of 14.3% and transmits serial data at 5.12 Gbps with a latency of less than 27.2 ns. LOCx2 is fabricated with a commercial 0.25-um Silicon-on-Sapphire CMOS technology and is packaged in a 100-pin QFN package. The power consumption of LOCx2 is about 843 mW.
A serializer ASIC and a VCSEL driver ASIC are needed for the front-end optical data transmission in the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25-{mu}m Silicon-on-Sapphire (SoS) CMOS technology and consumed 843 mW and 320 mW, respectively. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then of their counterparts, whereas other performance, such as the latency, data rate, and radiation tolerance, meet the phase-I upgrade requirements. We present the design of LOCx2-130 and LOCld-130. The test results of LOCx2-130 are also presented.
The construction of the ATLAS electromagnetic liquid argon calorimeter modules is completed and all the modules are assembled and inserted in the cryostats. During the production period four barrel and three endcap modules were exposed to test beams in order to assess their performance, ascertain the production quality and reproducibility, and to scrutinize the complete energy reconstruction chain from the readout and calibration electronics to the signal and energy reconstruction. It was also possible to check the full Monte Carlo simulation of the calorimeter. The analysis of the uniformity, resolution and extraction of constant term is presented. Typical non-uniformities of 0.5% and typical global constant terms of 0.6% are measured for the barrel and end-cap modules.
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