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Register a new userVisualization of Local Conductance in MoS2/WSe2 Heterostructure Transistors
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The vertical stacking of van der Waals (vdW) materials introduces a new degree of freedom to the research of two-dimensional (2D) systems. The interlayer coupling strongly influences the band structure of the heterostructures, resulting in novel properties that can be utilized for electronic and optoelectronic applications. Based on microwave microscopy studies, we report quantitative electrical imaging on gated molybdenum disulfide (MoS2)/tungsten diselenide (WSe2) heterostructure devices, which exhibit an intriguing anti-ambipolar effect in the transfer characteristics. Interestingly, in the region with significant source-drain current, electrons in the n-type MoS2 and holes in the p-type WSe2 segments are nearly balanced, whereas the heterostructure area is depleted of mobile charges. The configuration is analogous to the p-i-n diode, where the injected carriers dominate in the recombination current. The spatial evolution of local conductance can be ascribed to the lateral band bending and formation of depletion regions along the line of MoS2-heterostructure-WSe2. Our work vividly demonstrates the microscopic origin of novel transport behaviors, which is important for the vibrant field of vdW heterojunction research.
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Here, we propose a method to determine the thickness of the most common transition metal dichalcogenides (TMDCs) placed on the surface of transparent stamps, used for the deterministic placement of two-dimensional materials, by analyzing the red, green and blue channels of transmission-mode optical microscopy images of the samples. In particular, the blue channel transmittance shows a large and monotonic thickness dependence, making it a very convenient probe of the flake thickness. The method proved to be robust given the small flake-to-flake variation and the insensitivity to doping changes of MoS2. We also tested the method for MoSe2, WS2 and WSe2. These results provide a reference guide to identify the number of layers of this family of materials on transparent substrates only using optical microscopy.
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Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS$_2$ films at 560 C in 50 min, within the 450-to-600 C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ~140 $mathrm{{mu}A/{mu}m}$ at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS$_2$ grown below 600 C using solid-source precursors. The effective mobility from transfer length method test structures is $mathrm{29 pm 5 cm^2V^{-1}s^{-1}}$ at $mathrm{6.1 times 10^{12} cm^{-2}}$ electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.
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