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Register a new userPatterns and Thresholds of Magnetoelectric Switching in Spin Logic Devices
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In the quest to develop spintronic logic, it was discovered that magnetoelectric switching results in lower energy and shorter switching time than other mechanisms. Magnetoelectric (ME) field due to exchange bias at the interface with a multi-ferroic (such as BiFeO3) is well suited for 180 degree switching of magnetization. The ME field is determined by the direction of canted magnetization in BiFeO3 which can point at an angle to the plane, to which voltage is applied. Dependence of switching time and the threshold of ME field on its angles was determined by micromagnetic simulations. Switching occurs by formation of a domain wall on the side of the nanomagnet on top of BFO and its propagation to the rest of the magnet. For in-plane magnetization, switching occurs over a wide range of angles and at all magnitudes of ME field above threshold. For out-of-plane magnetization failure occurs (with an exception of a narrow range of angles and magnitudes of ME field) due to the domain wall reflecting from the opposite end of the nanomagnet.
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In this technical note, we address the comments on the energy estimates for Magnetoelectric Spin-orbit (MESO) Logic, a new logic device proposed by the authors. We provide an analytical derivation of the switching energy, and support it with time-domain circuit simulations using a self-consistent ferroelectric (FE) compact model. While the energy to charge a capacitor is dissipated in the interconnect and transistor resistance, we note that the energy to switch a capacitor and a FE is independent of the interconnect resistance value to the first order. Also device design can mitigate the parasitic energy losses. We further show the circuit simulations for a sub 10 aJ switching operation of a MESO logic device comprehending: a) Energy stored in multiferroic; b) Energy dissipation in the resistance of the interconnect, Ric ; c) Energy dissipation in the inverse spin-orbit coupling (ISOC) spin to charge converter Risoc; d) Supply, ground resistance, and transistor losses. We also identify the requirements for the resistivity of the spin-orbit coupling materials and address the effect of internal resistance of the spin to charge conversion layer. We provide the material parameter space where MESO (with a fan-out of 1 and interconnect) achieves sub 10 aJ switching energy with path for scaling via ferroelectric/magnetoelectric/spin-orbit materials development.
We propose the utilization of isotropic forward volume magneto-static spin waves in modern wave-based logic devices and suggest a concrete design for a spin-wave majority gate operating with these waves. We demonstrate by numerical simulations that the proposed out-of-plane magnetized majority gate overcomes the limitations of anisotropic in-plane magnetized majority gates due to the high spin-wave transmission through the gate, which enables a reduced energy consumption of these devices. Moreover, the functionality of the out-of-plane majority gate is increased due to the lack of parasitic generation of short-wavelength exchange spin waves.
We have studied the origin of switching (telegraph) noise at low temperature in lateral quantum structures defined electrostatically in GaAs/AlGaAs heterostructures by surface gates. The noise was measured by monitoring the conductance fluctuations around $e^2/h$ on the first step of a quantum point contact at around 1.2 K. Cooling with a positive bias on the gates dramatically reduces this noise, while an asymmetric bias exacerbates it. We propose a model in which the noise originates from a leakage current of electrons that tunnel through the Schottky barrier under the gate into the doped layer. The key to reducing noise is to keep this barrier opaque under experimental conditions. Bias cooling reduces the density of ionized donors, which builds in an effective negative gate voltage. A smaller negative bias is therefore needed to reach the desired operating point. This suppresses tunnelling from the gate and hence the noise. The reduction in the density of ionized donors also strengthens the barrier to tunneling at a given applied voltage. Support for the model comes from our direct observation of the leakage current into a closed quantum dot, around $10^{-20} mathrm{A}$ for this device. The current was detected by a neighboring quantum point contact, which showed monotonic steps in time associated with the tunneling of single electrons into the dot. If asymmetric gate voltages are applied, our model suggests that the noise will increase as a consequence of the more negative gate voltage applied to one of the gates to maintain the same device conductance. We observe exactly this behaviour in our experiments.
Magnetic analogue of electronic gates are advantageous in many ways. There is no electron leakage, higher switching speed and more energy saving in a magnetic logic device compared to a semiconductor one. Recently, we proposed a magnetic vortex transistor and fan-out out devices based on carefully coupled magnetic vortices in isolated nanomagnetic disks. Here, we demonstrate a new type of magnetic logic gate based upon asymmetric vortex transistor by using micromagnetic simulation. Depending upon two main features (topology) of magnetic vortex, chirality and polarity, the network can behave like a tri-state buffer. Considering the asymmetric magnetic vortex Transistor as a unit, the logic gate has been formed where two such transistors are placed parallel and another one is placed at the output. Magnetic energy given in the input transistors is transferred to the output transistor with giant amplification, due to the movement of antivortex solitons through the magnetic stray field. The loss and gain of energy at the output transistor can be controlled only by manipulating the polarities of the middle vortices in input transistors. Due to the asymmetric energy transfer of the antivortex solitons, we have shown successful fan-in operation in this topologically symmetric system. A tri-state buffer gate with fan-in of two transistors can be formed. This gate can be used as a Switch to the logic circuit and it has technological importance for energy transfer to large scale vortex networks.
We have measured the critical phase change conditions induced by electrical pulses in Ge2Sb2Te5 nanopillar phase change memory devices by constructing a comprehensive resistance map as a function of pulse parameters (width, amplitude and trailing edge). Our measurements reveal that the heating scheme and the details of the contact geometry play the dominant role in determining the final phase composition of the device such that a non-uniform heating scheme promotes partial amorphization/crystallization for a wide range of pulse parameters enabling multiple resistance levels for data storage applications. Furthermore we find that fluctuations in the snap-back voltage and set/reset resistances in repeated switching experiments are related to the details of the current distribution such that a uniform current injection geometry (i.e. circular contact) favors more reproducible switching parameters. This shows that possible geometrical defects in nanoscale phase change memory devices may play an essential role in the performance of the smallest possible devices through modification of the exact current distribution in the active chalcogenide layer. We present a three-dimensional finite element model of the electro-thermal physics to provide insights into the underlying physical mechanisms of the switching dynamics as well as to quantitatively account for the scaling behaviour of the switching currents in both circular and rectangular contact geometries. The calculated temporal evolution of the heat distribution within the pulse duration shows distinct features in rectangular contacts providing evidence for locally hot spots at the sharp corners of the current injection site due to current crowding effects leading to the observed behaviour.
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