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Register a new userTri-state Buffer: Magnetic Vortex Transistor Based Logic Devices
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Magnetic analogue of electronic gates are advantageous in many ways. There is no electron leakage, higher switching speed and more energy saving in a magnetic logic device compared to a semiconductor one. Recently, we proposed a magnetic vortex transistor and fan-out out devices based on carefully coupled magnetic vortices in isolated nanomagnetic disks. Here, we demonstrate a new type of magnetic logic gate based upon asymmetric vortex transistor by using micromagnetic simulation. Depending upon two main features (topology) of magnetic vortex, chirality and polarity, the network can behave like a tri-state buffer. Considering the asymmetric magnetic vortex Transistor as a unit, the logic gate has been formed where two such transistors are placed parallel and another one is placed at the output. Magnetic energy given in the input transistors is transferred to the output transistor with giant amplification, due to the movement of antivortex solitons through the magnetic stray field. The loss and gain of energy at the output transistor can be controlled only by manipulating the polarities of the middle vortices in input transistors. Due to the asymmetric energy transfer of the antivortex solitons, we have shown successful fan-in operation in this topologically symmetric system. A tri-state buffer gate with fan-in of two transistors can be formed. This gate can be used as a Switch to the logic circuit and it has technological importance for energy transfer to large scale vortex networks.
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Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10^5 for program and erase, write latency of 20ns with +/-2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10^10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.
We propose the utilization of isotropic forward volume magneto-static spin waves in modern wave-based logic devices and suggest a concrete design for a spin-wave majority gate operating with these waves. We demonstrate by numerical simulations that the proposed out-of-plane magnetized majority gate overcomes the limitations of anisotropic in-plane magnetized majority gates due to the high spin-wave transmission through the gate, which enables a reduced energy consumption of these devices. Moreover, the functionality of the out-of-plane majority gate is increased due to the lack of parasitic generation of short-wavelength exchange spin waves.
Traditional silicon binary circuits continue to face challenges such as high leakage power dissipation and large area of interconnections. Multiple-Valued Logic (MVL) and nano devices are two feasible solutions to overcome these problems. In this paper, a novel method is presented to design ternary logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs). The proposed designs use the unique properties of CNFETs, for example, adjusting the Carbon Nanontube (CNT) diameters to have the desired threshold voltage and have the same mobility of P-FET and N-FET transistors. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state which saves power while the circuits are not in use. In an effort to show a more detailed application of our approach, we design a 2-digit adder-subtractor circuit. We simulate the proposed ternary circuits using HSPICE via standard 32nm CNFET technology. The simulation results indicate the correct operation of the designs under different process, voltage and temperature (PVT) variations. Moreover, a power efficient ternary logic ALU has been design based on the proposed gates.
We demonstrate that the transition from the high-field state to the vortex state in a nanomagnetic disk shows the magnetic equivalent of supercooling. This is evidence that this magnetic transition can be described in terms of a modified Landau first-order phase transition. To accomplish this we have measured the bulk magnetization of single magnetic disks using nanomechanical torsional resonator torque magnetometry. This allows observation of single vortex creation events without averaging over an array of disks or over multiple runs.
In the quest to develop spintronic logic, it was discovered that magnetoelectric switching results in lower energy and shorter switching time than other mechanisms. Magnetoelectric (ME) field due to exchange bias at the interface with a multi-ferroic (such as BiFeO3) is well suited for 180 degree switching of magnetization. The ME field is determined by the direction of canted magnetization in BiFeO3 which can point at an angle to the plane, to which voltage is applied. Dependence of switching time and the threshold of ME field on its angles was determined by micromagnetic simulations. Switching occurs by formation of a domain wall on the side of the nanomagnet on top of BFO and its propagation to the rest of the magnet. For in-plane magnetization, switching occurs over a wide range of angles and at all magnitudes of ME field above threshold. For out-of-plane magnetization failure occurs (with an exception of a narrow range of angles and magnitudes of ME field) due to the domain wall reflecting from the opposite end of the nanomagnet.
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