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Register a new userCan Tunnel Transistors Scale Below 10nm?
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Added by
Hesameddin Ilatikhameneh
Publication date
2015
fields
Physics
and research's language is
English
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The main promise of tunnel FETs (TFETs) is to enable supply voltage ($V_{DD}$) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing $V_{DD}$ and channel length ($L_{ch}$) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high perfor]mance TFET with both low V$_{DD}$ ($sim$0.2V) and small $L_{ch}$ ($sim$6nm). In this work, it is shown that scaling TFETs in general requires scaling down the bandgap $E_g$ and scaling up the effective mass $m^*$ for high performance. Quantitatively, a channel material with an optimized bandgap ($E_gsim1.2qV_{DD} [eV]$) and an engineered effective mass ($m*^{-1}sim40 V_{DD}^{2.5} [m_0^{-1}]$) makes both $V_{DD}$ and $L_{ch}$ scaling feasible with the scaling rule of $L_{ch}/V_{DD}=30~nm/V$ for $L_{ch}$ from 15nm to 6nm and corresponding $V_{DD}$ from 0.5V to 0.2V.
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Tunneling field-effect transistors (TFETs) based on 2D materials are promising steep sub-threshold swing (SS) devices due to their tight gate control. There are two major methods to create the tunnel junction in these 2D TFETs: electrical and chemical doping. In this work, design guidelines for both electrically and chemically doped 2D TFETs are provided using full band atomistic quantum transport simulations in conjunction with analytic modeling. Moreover, several 2D TFETs performance boosters such as strain, source doping, and equivalent oxide thickness (EOT) are studied. Later on, these performance boosters are analyzed within a novel figure-of-merit plot (i.e. constant ON-current plot).
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