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Register a new userSubstrate Gating of Contact Resistance in Graphene Transistors
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Dionisis Berdebes Dionisis Berdebes
Publication date
2011
fields
Physics
and research's language is
English
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Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it was observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this letter, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. Our study indicates that the engineering of metal- graphene interface is a crucial step towards reducing the contact resistance for high performance graphene transistors.
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The paradigm of graphene transistors is based on the gate modulation of the channel carrier density by means of a local channel gate. This standard architecture is subject to the scaling limit of the channel length and further restrictions due to access and contact resistances impeding the device performance. We propose a novel design, overcoming these issues by implementing additional local gates underneath the contact region which allow a full control of the Klein barrier taking place at the contact edge. In particular, our work demonstrates the GHz operation of transistors driven by independent contact gates. We benchmark the standard channel and novel contact gating and report for the later dynamical transconductance levels at the state of the art. Our finding may find applications in electronics and optoelectronics whenever there is need to control independently the Fermi level and the electrostatic potential of electronic sources or to get rid of cumbersome local channel gates.
In this article, a novel two-path model is proposed to quantitatively explain sub-threshold characteristics of back-gated Schottky barrier FETs (SB-FETs) from 2D channel materials. The model integrates the conventional model for SB-FETs with the phenomenon of contact gating - an effect that significantly affects the carrier injection from the source electrode in back-gated field effect transistors. The two-path model is validated by a careful comparison with experimental characteristics obtained from a large number of back-gated WSe2 devices with various channel thicknesses. Our findings are believed to be of critical importance for the quantitative analysis of many three-terminal devices with ultrathin body channels.
We report a systematic study of the contact resistance present at the interface between a metal (Ti) and graphene layers of different, known thickness. By comparing devices fabricated on 11 graphene flakes we demonstrate that the contact resistance is quantitatively the same for single-, bi-, and tri-layer graphene ($sim800 pm 200 Omega mu m$), and is in all cases independent of gate voltage and temperature. We argue that the observed behavior is due to charge transfer from the metal, causing the Fermi level in the graphene region under the contacts to shift far away from the charge neutrality point.
We study the contact resistance and the transfer characteristics of back-gated field effect transistors of mono- and bi-layer graphene. We measure specific contact resistivity of ~7kohm*um2 and ~30kohm*um2 for Ni and Ti, respectively. We show that the contact resistance is a significant contributor to the total source-to-drain resistance and it is modulated by the back-gate voltage. We measure transfer characteristics showing double dip feature that we explain as the effect of doping due to charge transfer from the contacts causing minimum density of states for graphene under the contacts and in the channel at different gate voltage.
The extremely high carrier mobility and the unique band structure, make graphene very useful for field-effect transistor applications. According to several works, the primary limitation to graphene based transistor performance is not related to the material quality, but to extrinsic factors that affect the electronic transport properties. One of the most important parasitic element is the contact resistance appearing between graphene and the metal electrodes functioning as the source and the drain. Ohmic contacts to graphene, with low contact resistances, are necessary for injection and extraction of majority charge carriers to prevent transistor parameter fluctuations caused by variations of the contact resistance. The International Technology Roadmap for Semiconductors, toward integration and down-scaling of graphene electronic devices, identifies as a challenge the development of a CMOS compatible process that enables reproducible formation of low contact resistance. However, the contact resistance is still not well understood despite it is a crucial barrier towards further improvements. In this paper, we review the experimental and theoretical activity that in the last decade has been focusing on the reduction of the contact resistance in graphene transistors. We will summarize the specific properties of graphene-metal contacts with particular attention to the nature of metals, impact of fabrication process, Fermi level pinning, interface modifications induced through surface processes, charge transport mechanism, and edge contact formation.
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