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Register a new userDevelopment of a Detector Control System for the ATLAS Pixel Detector
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The innermost part of the ATLAS experiment will be a pixel detector containing around 1750 individual detector modules. A detector control system (DCS) is required to handle thousands of I/O channels with varying characteristics. The main building blocks of the pixel DCS are the cooling system, the power supplies and the thermal interlock system, responsible for the ultimate safety of the pixel sensors. The ATLAS Embedded Local Monitor Board (ELMB), a multi purpose front end I/O system with a CAN interface, is foreseen for several monitoring and control tasks. The Supervisory, Control And Data Acquisition (SCADA) system will use PVSS, a commercial software product chosen for the CERN LHC experiments. We report on the status of the different building blocks of the ATLAS pixel DCS.
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A pixel detector with high spatial resolution and temporal information for ultra-cold neutrons is developed based on a commercial CCD on which a neutron converter is attached. 10B and 6Li are tested for the neutron converter and 10B is found to be more suitable based on efficiency and spatial resolution. The pixel detector has an efficiency of 44.1 +- 1.1% and a spatial resolution of 2.9 +- 0.1 um (1 sigma).
This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in $200~nm$ SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionizing particle (MIP) tracking in particle physics experiments. For this reason few differe
To cope with the harsh environment foreseen at the high luminosity conditions of HL- LHC, the ATLAS pixel detector has to be upgraded to be fully efficient with a good granularity, a maximized geometrical acceptance and an high read out rate. LPNHE, FBK and INFN are involved in the development of thin and edgeless planar pixel sensors in which the insensitive area at the border of the sensor is minimized thanks to the active edge technology. In this paper we report on two productions, a first one consisting of 200 {mu}m thick n-on-p sensors with active edge, a second one composed of 100 and 130 {mu}m thick n-on-p sensors. Those sensors have been tested on beam, both at CERN-SPS and at DESY and their performance before and after irradiation will be presented.
This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver channels and a downstream transmitter channel. Each upstream channel operates at 5.12 Gbps, while the downstream channel operates at 2.56 Gbps. In each upstream channel, GBCR equalizes a signal received through a 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes the data with a recovered clock, and drives an optical transmitter. In the downstream channel, GBCR receives the data from an optical receiver and drives the same type of cable as the upstream channels. The output jitter of an upstream channel is 26.5 ps and the jitter of the downstream channel after the cable is 33.5 ps. Each upstream channel consumes 78 mW and each downstream channel consumes 27 mW. Simulation results of the upstream test channel suggest that a significant jitter reduction could be achieved with minimally increased power consumption by using a Feed Forward Equalizer (FFE) + Decision Feedback Equalization (DFE) in addition to the linear equalization of the baseline channel. GBCR is designed in a 65-nm CMOS technology.
We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated using different radioactive sources in an energy range from 6 to 40keV. In recent test beam experiments using 6GeV electrons, a signal-to-noise ratio of S/N~120 has been achieved with present sensors being 450 micron thick. For improved DEPFET systems using 50 micron thin sensors in future, a signal-to-noise of 40 is expected.
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