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Here we present the first demonstration and in-depth study of unreleased acoustic resonators in 14nm FinFET technology in the IEEE X band, which offer a zero-barrier-to-entry solution for high Q, small footprint, resonant tanks integrated seamlessly in advanced CMOS nodes. These devices leverage phononic waveguides for acoustic confinement, and exploit MOS capacitors and transistors inherent to the technology to electromechanically drive and sense acoustic vibrations. Sixteen device variations are analyzed across thirty bias points to discern the impact of phononic confinement, gate length, and termination scheme on resonator properties. The limiting factor in FinFET resonator performance among design variations tested is shown to be Back End of Line (BEOL) confinement, with devices with acoustic waveguides incorporating Mx and Cx metal layers exhibiting 2.2x higher average quality factor (Q) and peak amplitude, with maximum Q increasing from 115 to 181 and maximum amplitude scaling from 0.8 to 4.5 uS. A detailed analysis of biasing in the highest performing device shows good fit with a derived model, which addresses the velocity saturated piezoresistive effect for the first time in active resonant transistors. Peak differential transconductance that is dominated by changes in the silicon band-structure, as expected from an analysis that includes contributions from the piezoresistive effect, electrostatic modulation, and silicon bandgap modulation.
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Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18{mu}m standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18{mu}m standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of large and thin-oxide devices at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
The triple heterojunction TFET has been originally proposed to resolve TFETs low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full band atomistic NEGF approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode space approximation to simulate triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60mV/dec transfer characteristic under realistic scattering conditions.
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo- CMOS circuits implemented in a 28 nm FDSOI technology.
We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.
We report on the effects of ionizing radiation on 65nm CMOS transistors held at approximately -20C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.
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