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Register a new userThermionic charge transport in CMOS nano-transistors
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We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.
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Thermally activated sub-threshold transport has been investigated in undoped triple gate MOSFETs. The evolution of the barrier height and of the active cross-section area of the channel as a function of gate voltage has been determined. The results of our experiments and of the Tight Binding simulations we have developed are both in good agreement with previous analytical calculations, confirming the validity of thermionic approach to investigate transport in FETs. This method provides an important tool for the improvement of devices characteristics.
An indirect exciton is a bound state of an electron and a hole in spatially separated layers. Two-dimensional indirect excitons can be created optically in heterostructures containing double quantum wells or atomically thin semiconductors. We study theoretically transmission of such bosonic quasiparticles through nano-constrictions. We show that quantum transport phenomena, e.g., conductance quantization, single-slit diffraction, two-slit interference, and the Talbot effect, are experimentally realizable in systems of indirect excitons. We discuss similarities and differences between these phenomena and their counterparts in electronic devices.
Transient currents in atomically thin MoTe$_2$ field-effect transistor are measured during cycles of pulses through the gate electrode. The transients are analyzed in light of a newly proposed model for charge trapping dynamics that renders a time-dependent change in threshold voltage the dominant effect on the channel hysteretic behavior over emission currents from the charge traps. The proposed model is expected to be instrumental in understanding the fundamental physics that governs the performance of atomically thin FETs and is applicable to the entire class of atomically thin-based devices. Hence, the model is vital to the intelligent design of fast and highly efficient opto-electronic devices.
Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the Boltzmann tyranny that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a novel graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic cooling effect with the effective electron temperature of ~145 K in the monolayer MoS2, which enable the transport factor lowering and thus the steep-slope switching (across for 3 decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 {mu}A/{mu}m) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the great potential of 2D Dirac-source cold electron transistor as an innovative steep-slope transistor concept, and provides new opportunities for 2D materials toward future energy-efficient nanoelectronics.
At the LaAlO$_3$-SrTiO$_3$ interface, electronic phase transitions can be triggered by modulation of the charge carrier density, making this system an excellent prospect for the realization of versatile electronic devices. Here, we report repeatable transistor operation in locally gated LaAlO$_3$-SrTiO$_3$ field-effect devices of which the LaAlO$_3$ dielectric is only four unit cells thin, the critical thickness for conduction at this interface. This extremely thin dielectric allows a very efficient charge modulation of ${sim}3.2times10^{13}$ cm$^{-2}$ within a gate-voltage window of $pm1$ V, as extracted from capacitance-voltage measurements. These also reveal a large stray capacitance between gate and source, presenting a complication for nanoscale device operation. Despite the small LaAlO$_3$ thickness, we observe a negligible gate leakage current, which we ascribe to the extension of the conducting states into the SrTiO$_3$ substrate.
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