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Register a new userImpact of body thickness and scattering on III-V triple heterojunction Fin-TFET modeled with atomistic mode space approximation
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The triple heterojunction TFET has been originally proposed to resolve TFETs low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full band atomistic NEGF approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode space approximation to simulate triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60mV/dec transfer characteristic under realistic scattering conditions.
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Triple heterojunction (THJ) TFETs have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12 nm body thickness has poor performance, because its sub-threshold swing is 50 mV/dec and the ON-current is only 6 $mu A/mu m$. To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows a sub-threshold swing of 40 mV/dec over four orders of drain current and an ON-current of 325 uA/um with VGS = 0.3 V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design.
We propose a new triple-junction solar cell structure composed of a III-V heterojunction bipolar transistor solar cell (HBTSC) stacked on top of, and series-connected to, a Si solar cell (III-V-HBTSC-on-Si). The HBTSC is a novel three-terminal device, whose viability has been recently experimentally demonstrated. It has the theoretical efficiency limit of an independently-connected double-junction solar cell. Here, we perform detailed balance efficiency limit calculations under one-sun illumination that show that the absolute efficiency limit of a III-V-HBTSC-on-Si device is the same as for the conventional current-matched III-V-on-Si triple-junction (47% assuming black-body spectrum, 49% with AM1.5G). However, the range of band-gap energies for which the efficiency limit is above 40% is much wider in the III-V-HBTSC-on-Si stack case. From a technological point of view, the lattice-matched GaInP/GaAs combination is particularly interesting, which has an AM1.5G efficiency limit of 47% with the HBTSC-on-Si structure and 39% if the current-matched III-V-on-Si triple junction is considered. Moreover, we show that interconnecting the terminals of the HBTSC to achieve a two-terminal GaInP/GaAs-HBTSC-on-Si device only reduces the efficiency limit by three points, to 43%. As a result, the GaInP/GaAs-HBTSC-on-Si solar cell becomes a promising device for two-terminal, high-efficiency one-sun operation. For it to also be cost-effective, low-cost technologies must be applied to the III-V material growth, such as high-throughput epitaxy or sequential growth.
Here we present the first demonstration and in-depth study of unreleased acoustic resonators in 14nm FinFET technology in the IEEE X band, which offer a zero-barrier-to-entry solution for high Q, small footprint, resonant tanks integrated seamlessly in advanced CMOS nodes. These devices leverage phononic waveguides for acoustic confinement, and exploit MOS capacitors and transistors inherent to the technology to electromechanically drive and sense acoustic vibrations. Sixteen device variations are analyzed across thirty bias points to discern the impact of phononic confinement, gate length, and termination scheme on resonator properties. The limiting factor in FinFET resonator performance among design variations tested is shown to be Back End of Line (BEOL) confinement, with devices with acoustic waveguides incorporating Mx and Cx metal layers exhibiting 2.2x higher average quality factor (Q) and peak amplitude, with maximum Q increasing from 115 to 181 and maximum amplitude scaling from 0.8 to 4.5 uS. A detailed analysis of biasing in the highest performing device shows good fit with a derived model, which addresses the velocity saturated piezoresistive effect for the first time in active resonant transistors. Peak differential transconductance that is dominated by changes in the silicon band-structure, as expected from an analysis that includes contributions from the piezoresistive effect, electrostatic modulation, and silicon bandgap modulation.
The nonequilibrium Greens function (NEGF) method is often used to predict transport in atomistically resolved nanodevices and yields an immense numerical load when inelastic scattering on phonons is included. To ease this load, this work extends the atomistic mode space approach of Ref. [1] to include inelastic scattering on optical and acoustic phonons in silicon nanowires. This work also includes the exact calculation of the real part of retarded scattering self-energies in the reduced basis representation using the Kramers-Kronig relations. The inclusion of the Kramers-Kronig relation for the real part of the retarded scattering self-energy increases the impact of scattering. Virtually perfect agreement with results of the original representation is achieved with matrix rank reductions of more than 97%. Time-to-solution improvements of more than 200$times$ and peak memory reductions of more than 7$times$ are shown. This allows for the solution of electron transport scattered on phonons in atomically resolved nanowires with cross-sections larger than 5 nm $times$ 5 nm.
Heterostructures of two-dimensional (2D) and three-dimensional (3D) materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, we introduce a method to analyze measured capacitance-voltage data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors. We also demonstrate the accurate extraction of the built-in potential ($Phi$$_{bi}$) and the Schottky barrier height from the measurement data independent of the Richardson constant.
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