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Register a new userTowards field-programmable photonic gate arrays
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We review some of the basic principles, fundamentals, technologies, architectures and recent advances leading to thefor the implementation of Field Programmable Photonic Field Arrays (FPPGAs).
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This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC $180nm$ CMOS technology. The on-chip area and power dissipation of the simulated $3times 4$ TLG array is $1463 mu m^2$ and $425 mu W$, respectively.
A novel technique is presented for realising programmable silicon photonic circuits. Once the proposed photonic circuit is programmed, its routing is retained without the need for additional power consumption. This technology enables a uniform multi-purpose design of photonic chips for a range of different applications and performance requirements, as it can be programmed for each specific application after chip fabrication. Therefore the cost per chip can be dramatically reduced because of the increase in production volume, and rapid prototyping of new photonic circuits is enabled. Essential building blocks for programmable circuits, erasable directional couplers (DCs) were designed and fabricated, utilising ion implanted waveguides. We demonstrate permanent switching between the drop port and through port of the DCs using a localised post-fabrication laser annealing process. Proof-of-principle demonstrators in the form of generic 1X4 and 2X2 programmable switching circuits were then fabricated and subsequently programmed, to define their function.
Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to integrate on a tiny chip. However, these arrays may suffer from various manufacturing defects such as blockage and leakage in control and flow channels. Unfortunately, no efficient method is yet known for testing such a general-purpose architecture. In this paper, we present a novel formulation using the concept of flow paths and cut-sets, and describe an ILP-based hierarchical strategy for generating compact test sets that can detect multiple faults in FPVAs. Simulation results demonstrate the efficacy of the proposed method in detecting manufacturing faults with only a small number of test vectors.
Pipelined algorithms implemented in field programmable gate arrays are being extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms are increases rapidly. For development of such hardware triggers, algorithms are developed in $texttt{C++}$, ported to hardware description language for synthesizing firmware, and then ported back to $texttt{C++}$ for simulating the firmware response down to the single bit level. We present a $texttt{C++}$ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.
Programmable photonic circuits of reconfigurable interferometers can be used to implement arbitrary operations on optical modes, facilitating a flexible platform for accelerating tasks in quantum simulation, signal processing, and artificial intelligence. A major obstacle to scaling up these systems is static fabrication error, where small component errors within each device accrue to produce significant errors within the circuit computation. Mitigating this error usually requires numerical optimization dependent on real-time feedback from the circuit, which can greatly limit the scalability of the hardware. Here we present a deterministic approach to correcting circuit errors by locally correcting hardware errors within individual optical gates. We apply our approach to simulations of large scale optical neural networks and infinite impulse response filters implemented in programmable photonics, finding that they remain resilient to component error well beyond modern day process tolerances. Our results highlight a new avenue for scaling up programmable photonics to hundreds of modes within current day fabrication processes.
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