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Register a new userProgrammable Memristive Threshold Logic Gate Array
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Added by
Alex James Dr
Publication date
2018
fields
Informatics Engineering
and research's language is
English
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This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC $180nm$ CMOS technology. The on-chip area and power dissipation of the simulated $3times 4$ TLG array is $1463 mu m^2$ and $425 mu W$, respectively.
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