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Register a new userIII-V-on-silicon triple-junction based on the heterojunction bipolar transistor solar cell concept
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We propose a new triple-junction solar cell structure composed of a III-V heterojunction bipolar transistor solar cell (HBTSC) stacked on top of, and series-connected to, a Si solar cell (III-V-HBTSC-on-Si). The HBTSC is a novel three-terminal device, whose viability has been recently experimentally demonstrated. It has the theoretical efficiency limit of an independently-connected double-junction solar cell. Here, we perform detailed balance efficiency limit calculations under one-sun illumination that show that the absolute efficiency limit of a III-V-HBTSC-on-Si device is the same as for the conventional current-matched III-V-on-Si triple-junction (47% assuming black-body spectrum, 49% with AM1.5G). However, the range of band-gap energies for which the efficiency limit is above 40% is much wider in the III-V-HBTSC-on-Si stack case. From a technological point of view, the lattice-matched GaInP/GaAs combination is particularly interesting, which has an AM1.5G efficiency limit of 47% with the HBTSC-on-Si structure and 39% if the current-matched III-V-on-Si triple junction is considered. Moreover, we show that interconnecting the terminals of the HBTSC to achieve a two-terminal GaInP/GaAs-HBTSC-on-Si device only reduces the efficiency limit by three points, to 43%. As a result, the GaInP/GaAs-HBTSC-on-Si solar cell becomes a promising device for two-terminal, high-efficiency one-sun operation. For it to also be cost-effective, low-cost technologies must be applied to the III-V material growth, such as high-throughput epitaxy or sequential growth.
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Here we present the experimental results of an inverted three-terminal heterojunction bipolar transistor solar cell (HBTSC) made of GaInP/GaAs. The inverted growth and processing enable contacting the intermediate layer (base) from the bottom, which improves the cell performance by reducing shadow factor and series resistance at the same time. With this prototype we show that an inverted processing of a three-terminal solar cell is feasible and pave the way for the application of epitaxial lift-off, substrate reuse and mechanical stacking to the HBTSC which can eventually lead to a low-cost high-efficiency III-V-on-Si HBTSC technology.
Practical device architectures are proposed here for the implementation of three-terminal heterojunction bipolar transistor solar cells (3T-HBTSCs). These photovoltaic devices, which have a potential efficiency similar to that of multijunction cells, exhibit reduced spectral sensitivity compared with monolithically and series-connected tandem solar cells. In addition, the simplified n-p-n (or p-n-p) structure does not require the use of tunnel junctions. In this framework, four architectures are proposed and discussed in this paper: 1) one in which the top cell is based on silicon and the bottom cell is based on a heterojunction between silicon and III-V nanomaterials; 2) one in which the top cell is made of amorphous silicon and the bottom cell is made of an amorphous silicon-silicon heterojunction; 3) one based on the use of III-V semiconductors aimed at space applications; and 4) one in which the top cell is based on a perovskite material and the bottom cell is made of a perovskite-silicon heterostructure.
The triple heterojunction TFET has been originally proposed to resolve TFETs low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full band atomistic NEGF approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode space approximation to simulate triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60mV/dec transfer characteristic under realistic scattering conditions.
We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10-100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 {mu}W for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.
Heterostructures of two-dimensional (2D) and three-dimensional (3D) materials form efficient devices for utilizing the properties of both classes of materials. Graphene/silicon (G/Si) Schottky diodes have been studied extensively with respect to their optoelectronic properties. Here, we introduce a method to analyze measured capacitance-voltage data of G/Si Schottky diodes connected in parallel with G/silicon dioxide/Si (GIS) capacitors. We also demonstrate the accurate extraction of the built-in potential ($Phi$$_{bi}$) and the Schottky barrier height from the measurement data independent of the Richardson constant.
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