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Register a new userComputational ghost imaging using a field-programmable gate array
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Computational ghost imaging is a promising technique for single-pixel imaging because it is robust to disturbance and can be operated over broad wavelength bands, unlike common cameras. However, one disadvantage of this method is that it has a long calculation time for image reconstruction. In this paper, we have designed a dedicated calculation circuit that accelerated the process of computational ghost imaging. We implemented this circuit by using a field-programmable gate array, which reduced the calculation time for the circuit compared to a CPU. The dedicated circuit reconstructs images at a frame rate of 300 Hz.
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This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC $180nm$ CMOS technology. The on-chip area and power dissipation of the simulated $3times 4$ TLG array is $1463 mu m^2$ and $425 mu W$, respectively.
We introduced a new kind of patterns named Special-Hadamard patterns, which could be used as structured illuminations of computational ghost imaging. Special-Hadamard patterns can get a better image quality than Hadamard patterns in a noisy environment. We can completely reconstruct the original object in a noiseless environment by using Special-Hadamard patterns, and the size of object also can be adjusted arbitrarily, these advantages cannot be achieved by other common patterns. We also performed simulations to compare the results of Special Hadamard patterns with the results of Hadamard patterns. We found Special Hadamard patterns can greatly improve the image quality of computational ghost imaging.
This report describes a cantilever controller for magnetic resonance force microscopy (MRFM) based on a field programmable gate array (FPGA), along with the hardware and software used to integrate the controller into an experiment. The controller is assembled from a low-cost commercially available software defined radio (SDR) device and libraries of open-source software. The controller includes a digital filter comprising two cascaded second-order sections (biquads), which together can implement transfer functions for optimal cantilever controllers. An appendix in this report shows how to calculate filter coefficients for an optimal controller from measured cantilever characteristics. The controller also includes an input multiplexer and adder used in calibration protocols. Filter coefficients and multiplexer settings can be set and adjusted by control software while an experiment is running. The input is sampled at 64 MHz; the sampling frequency in the filters can be divided down under software control to achieve a good match with filter characterisics. Data reported here were sampled at 500 kHz, chosen for acoustic cantilevers with resonant frequencies near 8 kHz. Inputs are digitized with 12 bits resolution, outputs with 14 bits. The experiment software is organized as a client and server to make it easy to adapt the controller to different experiments. The server encapusulates the details of controller hardware organization, connection technology, filter architecture, and number representation. The same server could be used in any experiment, while a different client encodes the particulars of each experiment.
For decades, advances in electronics were directly driven by the scaling of CMOS transistors according to Moores law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits, and new computing architectures based on emerging devices, such as resistive random-access memory (RRAM) devices, are expected to sustain the exponential growth of computing capability. Here we propose a novel memory-centric, reconfigurable, general purpose computing platform that is capable of handling the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a uniform, physical, resistive, memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric for storage, arithmetic, and analog computing including neuromorphic computing tasks.
We describe the technological concept and the first-light results of a 1024-channel spectrometer based on field programmable gate array (FPGA) hardware. This spectrometer is the prototype for the seven beam L-band receiver to be installed at the Effelsberg 100-m telescope in autumn 2005. Using of-the-shelf hardware and software products, we designed and constructed an extremely flexible Fast-Fourier-Transform (FFT) spectrometer with unprecedented sensitivity and dynamic range, which can be considered prototypical for spectrometer development in future radio astronomy.
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