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Register a new userSuperconductor Electronics Fabrication Process with MoN$_x$ Kinetic Inductors and Self-Shunted Josephson Junctions
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Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth {lambda}$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, {lambda}$_0$ about 0.51 {mu}m, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/{mu}m$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers.
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Conventional Josephson metal-insulator-metal devices are inherently underdamped and exhibit hysteretic current-voltage response due to a very high subgap resistance compared to that in the normal state. At the same time, overdamped junctions with single-valued characteristics are needed for most superconducting digital applications. The usual way to overcome the hysteretic behavior is to place an external low-resistance normal-metal shunt in parallel with each junction. Unfortunately, such solution results in a considerable complication of the circuitry design and introduces parasitic inductance through the junction. This paper provides a concise overview of some generic approaches that have been proposed in order to realize internal shunting in Josephson heterostructures with a barrier that itself contains the desired resistive component. The main attention is paid to self-shunted devices with local weak-link transmission probabilities so strongly disordered in the interface plane that transmission probabilities are tiny for the main part of the transition region between two superconducting electrodes, while a small part of the interface is well transparent. We consider the possibility of realizing a universal bimodal distribution function and emphasize advantages of such junctions that can be considered as a new class of self-shunted Josephson devices promising for practical applications in superconducting electronics operating at 4.2 K.
We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 {mu}m made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.
We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFSS JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact {pi}-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 {mu}A/{mu}m^2 and 200 {mu}A/{mu}m^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and {pi}-junctions.
Magnetic flux quantization in superconductors allows the implementation of fast and energy-efficient digital superconducting circuits. However, the information representation in magnetic flux severely limits their functional density presenting a long-standing problem. Here we introduce a concept of superconducting digital circuits that do not utilize magnetic flux and have no inductors. We argue that neither the use of geometrical nor kinetic inductance is promising for the deep scaling of superconducting circuits. The key idea of our approach is the utilization of bistable Josephson junctions allowing the representation of information in their Josephson energy. Since the proposed circuits are composed of Josephson junctions only, they can be called all-Josephson junction (all-JJ) circuits. We present a methodology for the design of the circuits consisting of conventional and bistable junctions. We analyze the principles of the circuit functioning, ranging from simple logic cells and ending with an 8-bit parallel adder. The utilization of bistable junctions in the all-JJ circuits is promising in the aspects of simplification of schematics and the decrease of the JJ count leading to space-efficiency.
We present a cluster algorithm for resistively shunted Josephson junctions and similar physical systems, which dramatically improves sampling efficiency. The algorithm combines local updates in Fourier space with rejection-free cluster updates which exploit the symmetries of the Josephson coupling energy. As an application, we consider the localization transition of a single junction at intermediate Josephson coupling and determine the temperature dependence of the zero bias resistance as a function of dissipation strength.
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